From: Simon Marchi <simark@simark.ca>
To: Victor Collod <vcollod@nvidia.com>, gdb-patches@sourceware.org
Subject: Re: [PATCH] Improve intel IBT support
Date: Wed, 10 Jun 2020 23:18:50 -0400 [thread overview]
Message-ID: <0c2e7c13-3a10-0f83-955b-e08dcd628d17@simark.ca> (raw)
In-Reply-To: <20200605232314.9340-1-vcollod@nvidia.com>
On 2020-06-05 7:23 p.m., Victor Collod via Gdb-patches wrote:
> Refactor amd64_analyze_prologue to be more linear, add i386 support for endbr32.
Hi Victor,
Thanks for the patch. You mentioned this is your first submission; I see you've
used git-send-email, that's a very good start!
> 2020-03-12 Victor Collod <vcollod@nvidia.com>
>
> * i386-tdep.c (i386_skip_endbr): add a helper function to skip endbr
> instructions.
> (i386_analyze_prologue): call i386_skip_endbr.
> * amd64-tdep.c (amd64_analyze_prologue): make the function more linear
If I understand correctly, you are doing two orthogonal changes in this patch:
1- Change amd64_analyze_prologue to make it clearer / more readable (that's what I
understand by "more linear")
2. Add support for skipping another instruction
If that's the case, I think that can be a two patches series, such that each patch
has only one concern. This way, it's easier to convince ourself that each is correct.
Also, if a bug is introduced by one of the patches, it's easier to bisect and find
the culprit.
> ---
> gdb/amd64-tdep.c | 76 +++++++++++++++++++++++-------------------------
> gdb/i386-tdep.c | 19 ++++++++++++
> 2 files changed, 56 insertions(+), 39 deletions(-)
>
> diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
> index f96a9868259..06d0fe9a194 100644
> --- a/gdb/amd64-tdep.c
> +++ b/gdb/amd64-tdep.c
> @@ -2374,7 +2374,6 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
> CORE_ADDR pc, CORE_ADDR current_pc,
> struct amd64_frame_cache *cache)
> {
> - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
> /* The `endbr64` instruction. */
> static const gdb_byte endbr64[4] = { 0xf3, 0x0f, 0x1e, 0xfa };
> /* There are two variations of movq %rsp, %rbp. */
> @@ -2384,8 +2383,7 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
> static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 };
> static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec };
>
> - gdb_byte buf[3];
> - gdb_byte op;
> + gdb_byte buf[4];
>
> if (current_pc <= pc)
> return current_pc;
> @@ -2395,57 +2393,57 @@ amd64_analyze_prologue (struct gdbarch *gdbarch,
> else
> pc = amd64_analyze_stack_align (pc, current_pc, cache);
>
> - op = read_code_unsigned_integer (pc, 1, byte_order);
> + read_code (pc, buf, 4);
Just guessing, but I thought that the purpose of reading just one byte here
is so that if we're right at the end of a readable memory region, we won't
read too far. If read_code can't read the whole 4 bytes, it will throw an
exception.
> /* Check for the `endbr64` instruction, skip it if found. */
> - if (op == endbr64[0])
> + if (memcmp (buf, endbr64, sizeof(endbr64)) == 0)
Space after `sizeof`, happens a few times.
> diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c
> index e87d7f36356..f7670a7febb 100644
> --- a/gdb/i386-tdep.c
> +++ b/gdb/i386-tdep.c
> @@ -1537,6 +1537,24 @@ struct i386_insn i386_frame_setup_skip_insns[] =
> { 0 }
> };
>
> +/* Check whether PC points to an endbr32 instruction. */
> +static CORE_ADDR
> +i386_skip_endbr(CORE_ADDR pc)
Space before parenthesis.
Simon
next prev parent reply other threads:[~2020-06-11 3:18 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 23:23 Victor Collod
2020-06-05 23:55 ` Victor Collod
2020-06-11 3:18 ` Simon Marchi [this message]
2020-06-11 22:54 ` [PATCH v2 0/2] " Victor Collod
2020-06-11 22:54 ` [PATCH v2 1/2] Add i386 support for endbr skipping Victor Collod
2020-06-21 11:27 ` Simon Marchi
2020-06-11 22:54 ` [PATCH v2 2/2] Refactor amd64_analyze_prologue Victor Collod
2020-06-21 11:38 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 0/7] Improve intel IBT support Victor Collod
2020-06-24 1:28 ` [PATCH v3 1/7] Add i386 support for endbr skipping Victor Collod
2020-08-06 13:57 ` Simon Marchi
2020-09-19 0:29 ` [PATCH] gdb: Update i386_analyze_prologue to skip endbr32 H.J. Lu
2020-09-19 0:38 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 2/7] amd64_analyze_prologue: swap upper bound check condition operands Victor Collod
2020-08-06 14:41 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 3/7] amd64_analyze_prologue: merge op and buf Victor Collod
2020-08-06 14:55 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 4/7] amd64_analyze_prologue: invert a condition for readability Victor Collod
2020-08-06 14:57 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 5/7] amd64_analyze_prologue: gradually update pc Victor Collod
2020-08-06 14:59 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 6/7] amd64_analyze_prologue: fix incorrect comment Victor Collod
2020-08-06 15:05 ` Simon Marchi
2020-06-24 1:28 ` [PATCH v3 7/7] amd64_analyze_prologue: use target_read_code instead of read_code Victor Collod
2020-08-06 15:01 ` Simon Marchi
2020-08-05 21:44 ` [PATCH v3 0/7] Improve intel IBT support Victor Collod
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0c2e7c13-3a10-0f83-955b-e08dcd628d17@simark.ca \
--to=simark@simark.ca \
--cc=gdb-patches@sourceware.org \
--cc=vcollod@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox