Re: [PATCH v1] Intel(R) MPX registers to the DWARF enumeration.

[Joel Brobecker <brobecker@adacore.com>]

> Add registers as defined in the ABI adapted for MPX.
> As presented at:
> https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI
> 
> 2013-05-06  Walfred Tedeschi  <walfred.tedeschi@intel.com>
> 
>         * amd64-tdep.c (amd64_dwarf_regmap): Add mpx registers.
>         * amd64-tdep.h (amd64_regnum): Add mpx registers.

Small nit: should we spell "MPX"?

BTW - the ABI document reference above seem to only indicate
registers 126-129 as "reserved" rather than bound registers 0-4.
Is that normal?

> ---
>  gdb/amd64-tdep.c | 12 +++++++++++-
>  gdb/amd64-tdep.h |  3 ++-
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
> index f0720c8..0fa4d54 100644
> --- a/gdb/amd64-tdep.c
> +++ b/gdb/amd64-tdep.c
> @@ -233,7 +233,17 @@ static int amd64_dwarf_regmap[] =
>    /* Floating Point Control Registers.  */
>    AMD64_MXCSR_REGNUM,
>    AMD64_FCTRL_REGNUM,
> -  AMD64_FSTAT_REGNUM
> +  AMD64_FSTAT_REGNUM,
> +  -1, -1, -1, -1,                              /* 67 ... 70.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,      /* 70 ... 80.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,      /* 80 ... 90.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,      /* 90 ... 100.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,      /* 100 ... 110.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,      /* 110 ... 120.  */
> +  -1, -1, -1, -1, -1,                          /*120  ... 125.  */
> +
> +  AMD64_BND0R_REGNUM, AMD64_BND0R_REGNUM + 1,
> +  AMD64_BND0R_REGNUM + 2, AMD64_BND0R_REGNUM + 3

I'll admit this is a bit of a nitpicking, but I think it would
be useful to continue doing what we've been doing before,
which is document what the various range of register numbers
are for. And let's try to have them organized in banks of 8,
rather than 10.

Eg:

  /* MMX Registers 16 - 31 (67 - 82).  */
  -1, -1, -1, -1, -1, -1, -1, -1,
  -1, -1, -1, -1, -1, -1, -1, -1,

  /* Reserved (83 - 117).  */
  -1, -1, -1, -1, -1, -1, -1, -1,
  -1, -1, -1, -1, -1, -1, -1, -1,
  -1, -1, -1, -1, -1, -1, -1, -1,
  -1, -1, -1, -1, -1, -1, -1, -1,
  -1,

  /* Vector Mask Register 0 - 7 (118 - 125).  */
  -1, -1, -1, -1, -1, -1, -1, -1,

  /* Bound Registers 0 - 3 (126 - 129).  */
  AMD64_BND0R_REGNUM, AMD64_BND0R_REGNUM + 1,
  AMD64_BND0R_REGNUM + 2, AMD64_BND0R_REGNUM + 3,

(note that I added a comma at the end of the last register;
that way, if we add more later on, we don't have to modify
that line of code)

>  };
>  
>  static const int amd64_dwarf_regmap_len =
> diff --git a/gdb/amd64-tdep.h b/gdb/amd64-tdep.h
> index 704225e..76a89b9 100644
> --- a/gdb/amd64-tdep.h
> +++ b/gdb/amd64-tdep.h
> @@ -66,7 +66,8 @@ enum amd64_regnum
>    AMD64_YMM0H_REGNUM,          /* %ymm0h */
>    AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
>    AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
> -  AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
> +  AMD64_BND1R_REGNUM, AMD64_BND2R_REGNUM,
> +  AMD64_BND3R_REGNUM,
>    AMD64_BNDCFGU_REGNUM,
>    AMD64_BNDSTATUS_REGNUM,
>    AMD64_XMM16_REGNUM,
> -- 
> 2.1.4

-- 
Joel