[PATCH v1] Intel(R) MPX registers to the DWARF enumeration.

[Walfred Tedeschi <walfred.tedeschi@intel.com>]

Add registers as defined in the ABI adapted for MPX.
As presented at:
https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI

2013-05-06  Walfred Tedeschi  <walfred.tedeschi@intel.com>

	* amd64-tdep.c (amd64_dwarf_regmap): Add mpx registers.
	* amd64-tdep.h (amd64_regnum): Add mpx registers.

---
 gdb/amd64-tdep.c | 12 +++++++++++-
 gdb/amd64-tdep.h |  3 ++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index f0720c8..0fa4d54 100644
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -233,7 +233,17 @@ static int amd64_dwarf_regmap[] =
   /* Floating Point Control Registers.  */
   AMD64_MXCSR_REGNUM,
   AMD64_FCTRL_REGNUM,
-  AMD64_FSTAT_REGNUM
+  AMD64_FSTAT_REGNUM,
+  -1, -1, -1, -1,				/* 67 ... 70.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	/* 70 ... 80.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	/* 80 ... 90.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	/* 90 ... 100.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	/* 100 ... 110.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	/* 110 ... 120.  */
+  -1, -1, -1, -1, -1,				/*120  ... 125.  */
+
+  AMD64_BND0R_REGNUM, AMD64_BND0R_REGNUM + 1,
+  AMD64_BND0R_REGNUM + 2, AMD64_BND0R_REGNUM + 3
 };
 
 static const int amd64_dwarf_regmap_len =
diff --git a/gdb/amd64-tdep.h b/gdb/amd64-tdep.h
index 704225e..76a89b9 100644
--- a/gdb/amd64-tdep.h
+++ b/gdb/amd64-tdep.h
@@ -66,7 +66,8 @@ enum amd64_regnum
   AMD64_YMM0H_REGNUM,		/* %ymm0h */
   AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15,
   AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1,
-  AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3,
+  AMD64_BND1R_REGNUM, AMD64_BND2R_REGNUM,
+  AMD64_BND3R_REGNUM,
   AMD64_BNDCFGU_REGNUM,
   AMD64_BNDSTATUS_REGNUM,
   AMD64_XMM16_REGNUM,
-- 
2.1.4