From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 77966 invoked by alias); 26 Oct 2015 12:55:27 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 77911 invoked by uid 89); 26 Oct 2015 12:55:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: mga11.intel.com Received: from mga11.intel.com (HELO mga11.intel.com) (192.55.52.93) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 26 Oct 2015 12:55:21 +0000 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 26 Oct 2015 05:55:19 -0700 X-ExtLoop1: 1 Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga002.jf.intel.com with ESMTP; 26 Oct 2015 05:55:20 -0700 Received: from ulvlx001.iul.intel.com (ulvlx001.iul.intel.com [172.28.207.17]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id t9QCtHdh014792; Mon, 26 Oct 2015 12:55:17 GMT Received: from ulvlx001.iul.intel.com (localhost [127.0.0.1]) by ulvlx001.iul.intel.com with ESMTP id t9QCtHL5004911; Mon, 26 Oct 2015 13:55:17 +0100 Received: (from wtedesch@localhost) by ulvlx001.iul.intel.com with œ id t9QCtGBi004907; Mon, 26 Oct 2015 13:55:17 +0100 From: Walfred Tedeschi To: palves@redhat.com, brobecker@adacore.com Cc: gdb-patches@sourceware.org, Walfred Tedeschi Subject: [PATCH v1] Intel(R) MPX registers to the DWARF enumeration. Date: Mon, 26 Oct 2015 16:10:00 -0000 Message-Id: <1445864086-4831-5-git-send-email-walfred.tedeschi@intel.com> In-Reply-To: <1445864086-4831-1-git-send-email-walfred.tedeschi@intel.com> References: <1445864086-4831-1-git-send-email-walfred.tedeschi@intel.com> X-IsSubscribed: yes X-SW-Source: 2015-10/txt/msg00558.txt.bz2 Add registers as defined in the ABI adapted for MPX. As presented at: https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI 2013-05-06 Walfred Tedeschi * amd64-tdep.c (amd64_dwarf_regmap): Add mpx registers. * amd64-tdep.h (amd64_regnum): Add mpx registers. --- gdb/amd64-tdep.c | 12 +++++++++++- gdb/amd64-tdep.h | 3 ++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index f0720c8..0fa4d54 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -233,7 +233,17 @@ static int amd64_dwarf_regmap[] = /* Floating Point Control Registers. */ AMD64_MXCSR_REGNUM, AMD64_FCTRL_REGNUM, - AMD64_FSTAT_REGNUM + AMD64_FSTAT_REGNUM, + -1, -1, -1, -1, /* 67 ... 70. */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, /* 70 ... 80. */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, /* 80 ... 90. */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, /* 90 ... 100. */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, /* 100 ... 110. */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, /* 110 ... 120. */ + -1, -1, -1, -1, -1, /*120 ... 125. */ + + AMD64_BND0R_REGNUM, AMD64_BND0R_REGNUM + 1, + AMD64_BND0R_REGNUM + 2, AMD64_BND0R_REGNUM + 3 }; static const int amd64_dwarf_regmap_len = diff --git a/gdb/amd64-tdep.h b/gdb/amd64-tdep.h index 704225e..76a89b9 100644 --- a/gdb/amd64-tdep.h +++ b/gdb/amd64-tdep.h @@ -66,7 +66,8 @@ enum amd64_regnum AMD64_YMM0H_REGNUM, /* %ymm0h */ AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15, AMD64_BND0R_REGNUM = AMD64_YMM15H_REGNUM + 1, - AMD64_BND3R_REGNUM = AMD64_BND0R_REGNUM + 3, + AMD64_BND1R_REGNUM, AMD64_BND2R_REGNUM, + AMD64_BND3R_REGNUM, AMD64_BNDCFGU_REGNUM, AMD64_BNDSTATUS_REGNUM, AMD64_XMM16_REGNUM, -- 2.1.4