[RFA] Fix problem fetching/setting FSR register (IRIX)

[Joel Brobecker <brobecker@adacore.com>]

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Hello,

The attached patch fixes the problem reported at:
http://sources.redhat.com/ml/gdb-patches/2005-03/msg00294.html

The explaination of the actual problem is detailed at:
http://sources.redhat.com/ml/gdb-patches/2005-03/msg00309.html

I have also added some comments in the code, and included Mark's
comments.

2005-03-25  Joel Brobecker  <brobecker@adacore.com>

        * irix5-nat.c (supply_fpregset): Fix bug that caused the FSR
        register value to be incorrectly written in the regcache.
        (fill_fpregset): Fix bug that caused the FSR register value
        to be incorrectly read from the regcache.
        Fixes [E223-028].

Tested on mips-irix. No regression. OK to apply?

(I will submit a testcase for this asap)

Thanks,
-- 
Joel

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Index: irix5-nat.c
===================================================================
RCS file: /cvs/src/src/gdb/irix5-nat.c,v
retrieving revision 1.38
diff -u -p -r1.38 irix5-nat.c
--- irix5-nat.c	11 Feb 2005 04:05:56 -0000	1.38
+++ irix5-nat.c	26 Mar 2005 00:37:49 -0000
@@ -139,6 +139,7 @@ supply_fpregset (fpregset_t *fpregsetp)
 {
   int regi;
   static char zerobuf[32] = {0};
+  char fsrbuf[8];
 
   /* FIXME, this is wrong for the N32 ABI which has 64 bit FP regs. */
 
@@ -146,9 +147,17 @@ supply_fpregset (fpregset_t *fpregsetp)
     regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
 			 (char *) &fpregsetp->fp_r.fp_regs[regi]);
 
+  /* We can't supply the FSR register directly to the regcache,
+     because there is a size issue: On one hand, fpregsetp->fp_csr
+     is 32bits long, while the regcache expects a 64bits long value.
+     So we use a buffer of the correct size and copy into it the register
+     value at the proper location.  */
+  memset (fsrbuf, 0, 4);
+  memcpy (fsrbuf + 4, &fpregsetp->fp_csr, 4);
+
   regcache_raw_supply (current_regcache,
 		       mips_regnum (current_gdbarch)->fp_control_status,
-		       (char *) &fpregsetp->fp_csr);
+		       fsrbuf);
 
   /* FIXME: how can we supply FCRIR?  SGI doesn't tell us. */
   regcache_raw_supply (current_regcache,
@@ -173,11 +182,22 @@ fill_fpregset (fpregset_t *fpregsetp, in
 	}
     }
 
-  if ((regno == -1)
-      || (regno == mips_regnum (current_gdbarch)->fp_control_status))
-    regcache_raw_read (current_regcache,
-                       mips_regnum (current_gdbarch)->fp_control_status, 
-                       &fpregsetp->fp_csr);
+  if (regno == -1
+      || regno == mips_regnum (current_gdbarch)->fp_control_status)
+    {
+      char fsrbuf[8];
+
+      /* We can't fill the FSR register directly from the regcache,
+         because there is a size issue: On one hand, fpregsetp->fp_csr
+         is 32bits long, while the regcache expects a 64bits long buffer.
+         So we use a buffer of the correct size and copy the register
+         value from that buffer.  */
+      regcache_raw_read (current_regcache,
+                         mips_regnum (current_gdbarch)->fp_control_status,
+                         fsrbuf);
+
+      memcpy (&fpregsetp->fp_csr, fsrbuf + 4, 4);
+    }
 }