New port: CRISv32

New port: CRISv32

[Orjan Friberg]

Well, here it is.  The oft-talked-about, but never-yet-submitted one.  Since I 
am a CRIS maintainer and this only touches CRIS-specific files I assume I'm free 
to check this in, but in case anything is questionable (such as resurrecting the 
tm-cris.h file) and/or plain out wrong, here it is.

Oh, some recent gdb.base testsuite results:

# of expected passes            6240
# of unexpected failures        39
# of expected failures          6
# of known failures             5
# of unresolved testcases       1
# of untested testcases         1
# of unsupported tests          12


2005-01-15  Orjan Friberg  <orjanf@axis.com>

	* config/cris/tm-cris.h: Resurrect.
	(TARGET_HAS_HARDWARE_WATCHPOINTS, TARGET_CAN_USE_HARDWARE_WATCHPOINT)
	(TARGET_REGION_OK_FOR_HW_WATCHPOINT): Define.

	* cris-tdep.c (enum cris_num_regs, enum cris_regnums)
	(cris_sigtramp_frame_unwind_cache, cris_register_size): Update for
	CRISv32.
	(crisv32_single_step_through_delay, cris_can_use_hardware_watchpoint)
	(cris_region_ok_for_watchpoint, cris_stopped_data_address)
	(crisv32_cannot_fetch_register, crisv32_cannot_store_register)
	(crisv32_register_type, cris_special_register_name)
	(crisv32_register_name): New functions.
	(cris_spec_reg_applicable): Recognize more versions.
	(cris_register_name): Update with call to cris_special_register_name.
	(find_cris_op): Filter out CRISv32 instructions.  Tweaked comment and
	warning when unable to find step target.
	(CRISV10_ELF_NGREG, CRISV32_ELF_NGREG, crisv32_elf_gregset_t): Define.
	(supply_gregset): Add struct gdbarch_tdep.  Set pseudo-PC register for
	CRISv32.
	(fetch_core_registers): Update for CRISv32.
	(cris_gdbarch_init): Set pc_regnum, register_type, num_regs,
	register_name, cannot_store_register, cannot_fetch_register,
	have_nonsteppable_watchpoint, single_step_through_delay for CRISv32.


Resurrected file config/cris/tm-cris.h:

#include "solib.h"

extern int cris_can_use_hardware_watchpoint (int type, int count, int other);
extern int cris_region_ok_for_watchpoint (CORE_ADDR addr, int len);

#define TARGET_HAS_HARDWARE_WATCHPOINTS

#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, count, other) \
   cris_can_use_hardware_watchpoint (type, count, other)

#define TARGET_REGION_OK_FOR_HW_WATCHPOINT(addr, len) \
   cris_region_ok_for_watchpoint (addr, len)


Index: cris-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/cris-tdep.c,v
retrieving revision 1.120
diff -u -p -r1.120 cris-tdep.c
--- cris-tdep.c	13 Nov 2004 02:15:31 -0000	1.120
+++ cris-tdep.c	13 Jan 2005 15:38:03 -0000
@@ -56,7 +56,12 @@ enum cris_num_regs
    NUM_GENREGS = 16,

    /* There are 16 special registers.  */
-  NUM_SPECREGS = 16
+  NUM_SPECREGS = 16,
+
+  /* CRISv32 has a pseudo PC register, not noted here.  */
+
+  /* CRISv32 has 16 support registers.  */
+  NUM_SUPPREGS = 16
  };

  /* Register numbers of various important registers.
@@ -75,8 +80,9 @@ enum cris_num_regs
  enum cris_regnums
  {
    /* Enums with respect to the general registers, valid for all
-     CRIS versions.  */
+     CRIS versions.  The frame pointer is always in R8.  */
    CRIS_FP_REGNUM = 8,
+  /* ABI related registers.  */
    STR_REGNUM  = 9,
    RET_REGNUM  = 10,
    ARG1_REGNUM = 10,
@@ -84,23 +90,56 @@ enum cris_regnums
    ARG3_REGNUM = 12,
    ARG4_REGNUM = 13,

-  /* Enums with respect to the special registers, some of which may not be
-     applicable to all CRIS versions.  */
-  P0_REGNUM   = 16,
+  /* Registers which happen to be common.  */
    VR_REGNUM   = 17,
-  P2_REGNUM   = 18,
-  P3_REGNUM   = 19,
+  MOF_REGNUM  = 23,
+  SRP_REGNUM  = 27,
+
+  /* CRISv10 et. al. specific registers.  */
+  P0_REGNUM   = 16,
    P4_REGNUM   = 20,
    CCR_REGNUM  = 21,
-  MOF_REGNUM  = 23,
    P8_REGNUM   = 24,
    IBR_REGNUM  = 25,
    IRP_REGNUM  = 26,
-  SRP_REGNUM  = 27,
    BAR_REGNUM  = 28,
    DCCR_REGNUM = 29,
    BRP_REGNUM  = 30,
-  USP_REGNUM  = 31
+  USP_REGNUM  = 31,
+
+  /* CRISv32 specific registers.  */
+  ACR_REGNUM  = 15,
+  BZ_REGNUM   = 16,
+  PID_REGNUM  = 18,
+  SRS_REGNUM  = 19,
+  WZ_REGNUM   = 20,
+  EXS_REGNUM  = 21,
+  EDA_REGNUM  = 22,
+  DZ_REGNUM   = 24,
+  EBP_REGNUM  = 25,
+  ERP_REGNUM  = 26,
+  NRP_REGNUM  = 28,
+  CCS_REGNUM  = 29,
+  CRISV32USP_REGNUM  = 30, /* Shares name but not number with CRISv10.  */
+  SPC_REGNUM  = 31,
+  CRISV32PC_REGNUM   = 32, /* Shares name but not number with CRISv10.  */
+
+  S0_REGNUM = 33,
+  S1_REGNUM = 34,
+  S2_REGNUM = 35,
+  S3_REGNUM = 36,
+  S4_REGNUM = 37,
+  S5_REGNUM = 38,
+  S6_REGNUM = 39,
+  S7_REGNUM = 40,
+  S8_REGNUM = 41,
+  S9_REGNUM = 42,
+  S10_REGNUM = 43,
+  S11_REGNUM = 44,
+  S12_REGNUM = 45,
+  S13_REGNUM = 46,
+  S14_REGNUM = 47,
+  S15_REGNUM = 48,
  };

  extern const struct cris_spec_reg cris_spec_regs[];
@@ -311,20 +350,52 @@ cris_sigtramp_frame_unwind_cache (struct
  	unsigned long usp;
       }; */

-  /* R0 to R13 are stored in reverse order at offset (2 * 4) in
-     struct pt_regs.  */
-  for (i = 0; i <= 13; i++)
-    info->saved_regs[i].addr = addr + ((15 - i) * 4);
-
-  info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
-  info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
-  info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
-  /* Note: IRP is off by 2 at this point.  There's no point in correcting it
-     though since that will mean that the backtrace will show a PC different
-     from what is shown when stopped.  */
-  info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
-  info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM];
-  info->saved_regs[SP_REGNUM].addr = addr + (24 * 4);
+  if (tdep->cris_version == 10)
+    {
+      /* R0 to R13 are stored in reverse order at offset (2 * 4) in
+	 struct pt_regs.  */
+      for (i = 0; i <= 13; i++)
+	info->saved_regs[i].addr = addr + ((15 - i) * 4);
+
+      info->saved_regs[MOF_REGNUM].addr = addr + (16 * 4);
+      info->saved_regs[DCCR_REGNUM].addr = addr + (17 * 4);
+      info->saved_regs[SRP_REGNUM].addr = addr + (18 * 4);
+      /* Note: IRP is off by 2 at this point.  There's no point in correcting
+	 it though since that will mean that the backtrace will show a PC
+	 different from what is shown when stopped.  */
+      info->saved_regs[IRP_REGNUM].addr = addr + (19 * 4);
+      info->saved_regs[PC_REGNUM] = info->saved_regs[IRP_REGNUM];
+      info->saved_regs[SP_REGNUM].addr = addr + (24 * 4);
+    }
+  else
+    {
+      /* CRISv32.  */
+      /* R0 to R13 are stored in order at offset (1 * 4) in
+	 struct pt_regs.  */
+      for (i = 0; i <= 13; i++)
+	info->saved_regs[i].addr = addr + ((i + 1) * 4);
+
+      info->saved_regs[ACR_REGNUM].addr = addr + (15 * 4);
+      info->saved_regs[SRS_REGNUM].addr = addr + (16 * 4);
+      info->saved_regs[MOF_REGNUM].addr = addr + (17 * 4);
+      info->saved_regs[SPC_REGNUM].addr = addr + (18 * 4);
+      info->saved_regs[CCS_REGNUM].addr = addr + (19 * 4);
+      info->saved_regs[SRP_REGNUM].addr = addr + (20 * 4);
+      info->saved_regs[ERP_REGNUM].addr = addr + (21 * 4);
+      info->saved_regs[EXS_REGNUM].addr = addr + (22 * 4);
+      info->saved_regs[EDA_REGNUM].addr = addr + (23 * 4);
+
+      /* FIXME: If ERP is in a delay slot at this point then the PC will
+	 be wrong at this point.  This problem manifests itself in the
+	 sigaltstack.exp test case, which occasionally generates FAILs when
+	 the signal is received while in a delay slot.
+	
+	 This could be solved by a couple of read_memory_unsigned_integer and a
+	 trad_frame_set_value.  */
+      info->saved_regs[PC_REGNUM] = info->saved_regs[ERP_REGNUM];
+
+      info->saved_regs[SP_REGNUM].addr = addr + (25 * 4);
+    }

    return info;
  }
@@ -375,7 +446,72 @@ cris_sigtramp_frame_sniffer (struct fram
    return NULL;
  }

+int
+crisv32_single_step_through_delay (struct gdbarch *gdbarch,
+				   struct frame_info *this_frame)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  ULONGEST erp;
+  int ret = 0;
+  char buf[4];
+
+  frame_unwind_register (this_frame, ERP_REGNUM, buf);
+  erp = extract_unsigned_integer (buf, 4);
+
+  if (erp & 0x1)
+    {
+      /* In delay slot - check if there's a breakpoint at the preceding
+	 instruction.  */
+      if (breakpoint_here_p (erp & ~0x1))
+	ret = 1;
+    }
+  return ret;
+}
+
+/* Hardware watchpoint support.  */
+
+/* We support 6 hardware data watchpoints, but cannot trigger on execute
+   (any combination of read/write is fine).  */
+
+int
+cris_can_use_hardware_watchpoint (int type, int count, int other)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  /* No bookkeeping is done here; it is handled by the remote debug agent.  */
+
+  if (tdep->cris_version != 32)
+    return 0;
+  else
+    /* CRISv32: Six data watchpoints, one for instructions.  */
+    return (((type == bp_read_watchpoint || type == bp_access_watchpoint
+	     || type == bp_hardware_watchpoint) && count <= 6)
+	    || (type == bp_hardware_breakpoint && count <= 1));
+}
+
+/* The CRISv32 hardware data watchpoints work by specifying ranges,
+   which have no alignment or length restrictions.  */
+
+int
+cris_region_ok_for_watchpoint (CORE_ADDR addr, int len)
+{
+  return 1;
+}
+
+/* If the inferior has some watchpoint that triggered, return the
+   address associated with that watchpoint.  Otherwise, return
+   zero.  */
+
+CORE_ADDR
+cris_stopped_data_address (void)
+{
+  CORE_ADDR eda;
+  eda = read_register (EDA_REGNUM);
+  return eda;
+}
+
  /* The instruction environment needed to find single-step breakpoints.  */
+
  typedef
  struct instruction_environment
  {
@@ -1286,8 +1422,18 @@ cris_spec_reg_applicable (struct cris_sp
        return (version == 8 || version == 9);
      case cris_ver_v8p:
        return (version >= 8);
+    case cris_ver_v0_10:
+      return (version >= 0 && version <= 10);
+    case cris_ver_v3_10:
+      return (version >= 3 && version <= 10);
+    case cris_ver_v8_10:
+      return (version >= 8 && version <= 10);
+    case cris_ver_v10:
+      return (version == 10);
      case cris_ver_v10p:
        return (version >= 10);
+    case cris_ver_v32p:
+      return (version >= 32);
      default:
        /* Invalid cris version.  */
        return 0;
@@ -1300,6 +1446,7 @@ cris_spec_reg_applicable (struct cris_sp
  static int
  cris_register_size (int regno)
  {
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
    int i;
    int spec_regno;

@@ -1308,15 +1455,13 @@ cris_register_size (int regno)
        /* General registers (R0 - R15) are 32 bits.  */
        return 4;
      }
-  else if (regno >= NUM_GENREGS && regno < NUM_REGS)
+  else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
      {
        /* Special register (R16 - R31).  cris_spec_regs is zero-based.
           Adjust regno accordingly.  */
        spec_regno = regno - NUM_GENREGS;

-      /* The entries in cris_spec_regs are stored in register number order,
-         which means we can shortcut into the array when searching it.  */
-      for (i = spec_regno; cris_spec_regs[i].name != NULL; i++)
+      for (i = 0; cris_spec_regs[i].name != NULL; i++)
          {
            if (cris_spec_regs[i].number == spec_regno
                && cris_spec_reg_applicable (cris_spec_regs[i]))
@@ -1326,11 +1471,15 @@ cris_register_size (int regno)
        /* Special register not applicable to this CRIS version.  */
        return 0;
      }
-  else
+  else if (regno >= PC_REGNUM && regno < NUM_REGS)
      {
-      /* Invalid register.  */
-      return -1;
+      /* This will apply to CRISv32 only where there are additional registers
+	 after the special registers (pseudo PC and support registers).  */
+      return 4;
      }
+
+
+  return -1;
  }

  /* Nonzero if regno should not be fetched from the target.  This is the case
@@ -1373,6 +1522,46 @@ cris_cannot_store_register (int regno)
    return 0;
  }

+/* Nonzero if regno should not be fetched from the target.  This is the case
+   for unimplemented (size 0) and non-existant registers.  */
+
+static int
+crisv32_cannot_fetch_register (int regno)
+{
+  return ((regno < 0 || regno >= NUM_REGS)
+          || (cris_register_size (regno) == 0));
+}
+
+/* Nonzero if regno should not be written to the target, for various
+   reasons.  */
+
+static int
+crisv32_cannot_store_register (int regno)
+{
+  /* There are three kinds of registers we refuse to write to.
+     1. Those that not implemented.
+     2. Those that are read-only (depends on the processor mode).
+     3. Those registers to which a write has no effect.
+  */
+
+  if (regno < 0 || regno >= NUM_REGS || cris_register_size (regno) == 0)
+    /* Not implemented.  */
+    return 1;
+
+  else if  (regno == VR_REGNUM)
+    /* Read-only.  */
+    return 1;
+
+  else if  (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM)
+    /* Writing has no effect.  */
+    return 1;
+
+  /* Many special registers are read-only in user mode.  Let the debug
+     agent decide whether they are writable.  */
+
+  return 0;
+}
+
  /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type
     of data in register regno.  */

@@ -1396,6 +1585,32 @@ cris_register_type (struct gdbarch *gdba
        return builtin_type_int0;
  }

+static struct type *
+crisv32_register_type (struct gdbarch *gdbarch, int regno)
+{
+  if (regno == PC_REGNUM)
+    return builtin_type_void_func_ptr;
+  else if (regno == SP_REGNUM || regno == CRIS_FP_REGNUM)
+    return builtin_type_void_data_ptr;
+  else if ((regno >= 0 && regno <= ACR_REGNUM)
+	   || (regno >= EXS_REGNUM && regno <= SPC_REGNUM)
+	   || (regno == PID_REGNUM)
+	   || (regno >= S0_REGNUM && regno <= S15_REGNUM))
+    /* Note: R8 and SP taken care of by previous clause.  */
+    return builtin_type_uint32;
+  else if (regno == WZ_REGNUM)
+      return builtin_type_uint16;
+  else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM)
+      return builtin_type_uint8;
+  else
+    {
+      /* Invalid (unimplemented) register.  Should not happen as there are
+	 no unimplemented CRISv32 registers.  */
+      warning ("crisv32_register_type: unknown regno %d", regno);
+      return builtin_type_int0;
+    }
+}
+
  /* Stores a function return value of type type, where valbuf is the address
     of the value to be stored.  */

@@ -1430,6 +1645,29 @@ cris_store_return_value (struct type *ty
     unimplemented register.  */

  static const char *
+cris_special_register_name (int regno)
+{
+  int spec_regno;
+  int i;
+
+  /* Special register (R16 - R31).  cris_spec_regs is zero-based.
+     Adjust regno accordingly.  */
+  spec_regno = regno - NUM_GENREGS;
+
+  /* Assume nothing about the layout of the cris_spec_regs struct
+     when searching.  */
+  for (i = 0; cris_spec_regs[i].name != NULL; i++)
+    {
+      if (cris_spec_regs[i].number == spec_regno
+	  && cris_spec_reg_applicable (cris_spec_regs[i]))
+	/* Go with the first applicable register.  */
+	return cris_spec_regs[i].name;
+    }
+  /* Special register not applicable to this CRIS version.  */
+  return NULL;
+}
+
+static const char *
  cris_register_name (int regno)
  {
    static char *cris_genreg_names[] =
@@ -1438,9 +1676,6 @@ cris_register_name (int regno)
      "r8",  "r9",  "r10", "r11", \
      "r12", "r13", "sp",  "pc" };

-  int i;
-  int spec_regno;
-
    if (regno >= 0 && regno < NUM_GENREGS)
      {
        /* General register.  */
@@ -1448,22 +1683,49 @@ cris_register_name (int regno)
      }
    else if (regno >= NUM_GENREGS && regno < NUM_REGS)
      {
-      /* Special register (R16 - R31).  cris_spec_regs is zero-based.
-         Adjust regno accordingly.  */
-      spec_regno = regno - NUM_GENREGS;
-
-      /* The entries in cris_spec_regs are stored in register number order,
-         which means we can shortcut into the array when searching it.  */
-      for (i = spec_regno; cris_spec_regs[i].name != NULL; i++)
-        {
-          if (cris_spec_regs[i].number == spec_regno
-              && cris_spec_reg_applicable (cris_spec_regs[i]))
-            /* Go with the first applicable register.  */
-            return cris_spec_regs[i].name;
-        }
-      /* Special register not applicable to this CRIS version.  */
+      return cris_special_register_name (regno);
+    }
+  else
+    {
+      /* Invalid register.  */
        return NULL;
      }
+}
+
+static const char *
+crisv32_register_name (int regno)
+{
+  static char *crisv32_genreg_names[] =
+    { "r0",  "r1",  "r2",  "r3", \
+      "r4",  "r5",  "r6",  "r7", \
+      "r8",  "r9",  "r10", "r11", \
+      "r12", "r13", "sp",  "acr"
+    };
+
+  static char *crisv32_sreg_names[] =
+    { "s0",  "s1",  "s2",  "s3", \
+      "s4",  "s5",  "s6",  "s7", \
+      "s8",  "s9",  "s10", "s11", \
+      "s12", "s13", "s14",  "s15"
+    };
+
+  if (regno >= 0 && regno < NUM_GENREGS)
+    {
+      /* General register.  */
+      return crisv32_genreg_names[regno];
+    }
+  else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS))
+    {
+      return cris_special_register_name (regno);
+    }
+  else if (regno == PC_REGNUM)
+    {
+      return "pc";
+    }
+  else if (regno >= S0_REGNUM && regno <= S15_REGNUM)
+    {
+      return crisv32_sreg_names[regno - S0_REGNUM];
+    }
    else
      {
        /* Invalid register.  */
@@ -1685,7 +1947,9 @@ find_cris_op (unsigned short insn, inst_
    for (i = 0; cris_opcodes[i].name != NULL; i++)
      {
        if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match)
-          && ((cris_opcodes[i].lose & insn) == 0))
+          && ((cris_opcodes[i].lose & insn) == 0)
+	  /* Only CRISv10 instructions, please.  */
+	  && (cris_opcodes[i].applicable_version != cris_ver_v32p))
          {
            level_of_match = constraint (insn, cris_opcodes[i].args, inst_env);
            if (level_of_match >= 0)
@@ -1788,8 +2052,9 @@ cris_software_single_step (enum target_s
        int status = find_step_target (&inst_env);
        if (status == -1)
          {
-          /* Could not find a target.  FIXME: Should do something.  */
-          warning ("cris_software_single_step: unable to find step target");
+          /* Could not find a target.  Things are likely to go downhill
+	     from here.  */
+	  warning ("CRIS software single step could not find a step target.");
          }
        else
          {
@@ -3515,13 +3780,18 @@ cris_delayed_get_disassembler (bfd_vma a
  typedef unsigned long elf_greg_t;

  /* Same as user_regs_struct struct in <asm/user.h>.  */
-typedef elf_greg_t elf_gregset_t[35];
+#define CRISV10_ELF_NGREG 35
+typedef elf_greg_t elf_gregset_t[CRISV10_ELF_NGREG];
+
+#define CRISV32_ELF_NGREG 32
+typedef elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG];

  /* Unpack an elf_gregset_t into GDB's register cache.  */

  static void
  supply_gregset (elf_gregset_t *gregsetp)
  {
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
    int i;
    elf_greg_t *regp = *gregsetp;
    static char zerobuf[4] = {0};
@@ -3532,6 +3802,18 @@ supply_gregset (elf_gregset_t *gregsetp)
      {
        regcache_raw_supply (current_regcache, i, (char *)&regp[i]);
      }
+
+  if (tdep->cris_version == 32)
+    {
+      /* Needed to set pseudo-register PC for CRISv32.  */
+      /* FIXME: If ERP is in a delay slot at this point then the PC will
+	 be wrong.  Issue a warning to alert the user.  */
+      regcache_raw_supply (current_regcache, PC_REGNUM,
+			   (char *)&regp[ERP_REGNUM]);
+
+      if (*(char *)&regp[ERP_REGNUM] & 0x1)
+	fprintf_unfiltered (gdb_stderr, "Warning: PC in delay slot\n");
+    }
  }

  /*  Use a local version of this function to get the correct types for
@@ -3546,7 +3828,8 @@ fetch_core_registers (char *core_reg_sec
    switch (which)
      {
      case 0:
-      if (core_reg_size != sizeof (gregset))
+      if (core_reg_size != sizeof (elf_gregset_t)
+	  && core_reg_size != sizeof (crisv32_elf_gregset_t))
          {
            warning ("wrong size gregset struct in core file");
          }
@@ -3706,6 +3989,10 @@ cris_gdbarch_init (struct gdbarch_info i
        /* Trust the user's CRIS version setting.  */
        cris_version = usr_cmd_cris_version;
      }
+  else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32)
+    {
+      cris_version = 32;
+    }
    else
      {
        /* Assume it's CRIS version 10.  */
@@ -3755,18 +4042,16 @@ cris_gdbarch_init (struct gdbarch_info i
  					      cris_reg_struct_has_addr);
    set_gdbarch_deprecated_use_struct_convention (gdbarch, 
always_use_struct_convention);

-  /* There are 32 registers (some of which may not be implemented).  */
-  set_gdbarch_num_regs (gdbarch, 32);
    set_gdbarch_sp_regnum (gdbarch, 14);
-  set_gdbarch_pc_regnum (gdbarch, 15);
-  set_gdbarch_register_name (gdbarch, cris_register_name);
+
+  /* Length of ordinary registers used in push_word and a few other
+     places.  register_size() is the real way to know how big a
+     register is.  */

    set_gdbarch_double_bit (gdbarch, 64);
    /* The default definition of a long double is 2 * TARGET_DOUBLE_BIT,
       which means we have to set this explicitly.  */
-  set_gdbarch_long_double_bit (gdbarch, 64);
-  set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
-  set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
+  set_gdbarch_long_double_bit (gdbarch, 64);

    /* The total amount of space needed to store (in an array called registers)
       GDB's copy of the machine's register state.  Note: We can not use
@@ -3789,20 +4074,49 @@ cris_gdbarch_init (struct gdbarch_info i
      case 11:
        /* CRIS v10 and v11, a.k.a. ETRAX 100LX.  In addition to ETRAX 100,
           P7 (32 bits), and P15 (32 bits) have been implemented.  */
+      set_gdbarch_pc_regnum (gdbarch, 15);
+      set_gdbarch_register_type (gdbarch, cris_register_type);
+      /* There are 32 registers (some of which may not be implemented).  */
+      set_gdbarch_num_regs (gdbarch, 32);
+      set_gdbarch_register_name (gdbarch, cris_register_name);
+      set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register);
+      set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register);
+
+      set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
+      break;
+
+    case 32:
+      /* CRIS v32.  General registers R0 - R15 (32 bits), special registers
+	 P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits)
+	 and pseudo-register PC (32 bits).  */
+      set_gdbarch_pc_regnum (gdbarch, 32);
+      set_gdbarch_register_type (gdbarch, crisv32_register_type);
+      /* 32 registers + pseudo-register PC + 16 support registers.  */
+      set_gdbarch_num_regs (gdbarch, 32 + 1 + 16);
+      set_gdbarch_register_name (gdbarch, crisv32_register_name);
+
+      set_gdbarch_cannot_store_register
+	(gdbarch, crisv32_cannot_store_register);
+      set_gdbarch_cannot_fetch_register
+	(gdbarch, crisv32_cannot_fetch_register);
+
+      set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
+
+      set_gdbarch_single_step_through_delay
+	(gdbarch, crisv32_single_step_through_delay);
+
        break;

      default:
-      internal_error (__FILE__, __LINE__, "cris_gdbarch_init: unknown CRIS 
version");
+      internal_error (__FILE__, __LINE__,
+		      "cris_gdbarch_init: unknown CRIS version");
      }

-  set_gdbarch_register_type (gdbarch, cris_register_type);
-
-  /* Dummy frame functions.  */
+  /* Dummy frame functions (shared between CRISv10 and CRISv32 since they
+     have the same ABI).  */
    set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code);
    set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call);
    set_gdbarch_frame_align (gdbarch, cris_frame_align);
-
-  set_gdbarch_software_single_step (gdbarch, cris_software_single_step);
    set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue);

    /* The stack grows downward.  */

-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Andrew Cagney]

Orjan Friberg wrote:
> Well, here it is.  The oft-talked-about, but never-yet-submitted one.  
> Since I am a CRIS maintainer and this only touches CRIS-specific files I 
> assume I'm free to check this in, but in case anything is questionable 
> (such as resurrecting the tm-cris.h file) and/or plain out wrong, here 
> it is.
> 
> Oh, some recent gdb.base testsuite results:
> 
> # of expected passes            6240
> # of unexpected failures        39
> # of expected failures          6
> # of known failures             5
> # of unresolved testcases       1
> # of untested testcases         1
> # of unsupported tests          12
> 
> 
> 2005-01-15  Orjan Friberg  <orjanf@axis.com>
> 
>     * config/cris/tm-cris.h: Resurrect.
>     (TARGET_HAS_HARDWARE_WATCHPOINTS, TARGET_CAN_USE_HARDWARE_WATCHPOINT)
>     (TARGET_REGION_OK_FOR_HW_WATCHPOINT): Define.

Yep, bear trap.

You'll see that MarkK's being elimiating the TM files and the TM_FILE 
macro is now deprecated (and you can't add deprecated stuff :-)

We're going to need to figure out how to fix things so that these macros 
are avoided.

Andrew

Re: New port: CRISv32

[Orjan Friberg]

Andrew Cagney wrote:
> Orjan Friberg wrote:
>>
>> 2005-01-15  Orjan Friberg  <orjanf@axis.com>
>>
>>     * config/cris/tm-cris.h: Resurrect.
>>     (TARGET_HAS_HARDWARE_WATCHPOINTS, TARGET_CAN_USE_HARDWARE_WATCHPOINT)
>>     (TARGET_REGION_OK_FOR_HW_WATCHPOINT): Define.

[snip]

> We're going to need to figure out how to fix things so that these macros 
> are avoided.

Could something as straightforward as this be the answer?  (gdbarch.[hc] diffs 
not included.)

2005-01-25  Orjan Friberg  <orjanf@axis.com>

	* gdbarch.sh (target_has_hardware_watchpoints)
	(target_can_use_hardware_watchpoint, target_region_ok_for_watchpoint):
	Add.
         * gdbarch.h: Re-generate.
	* gdbarch.c: Ditto.


Index: gdbarch.sh
===================================================================
RCS file: /cvs/src/src/gdb/gdbarch.sh,v
retrieving revision 1.352
diff -u -r1.352 gdbarch.sh
--- gdbarch.sh  3 Dec 2004 23:59:52 -0000       1.352
+++ gdbarch.sh  25 Jan 2005 14:25:33 -0000
@@ -650,7 +650,10 @@
  f:=:void:coff_make_msymbol_special:int val, struct minimal_symbol *msym:val, 
msym::default_coff_make_msymbol_special::0
  v:=:const char *:name_of_malloc:::"malloc":"malloc"::0:NAME_OF_MALLOC
  v:=:int:cannot_step_breakpoint:::0:0::0
+v:=:int:target_has_hardware_watchpoints:::0:0::0
  v:=:int:have_nonsteppable_watchpoint:::0:0::0
+f:=:int:target_can_use_hardware_watchpoint:int type, int count, int other:type, 
count, other
+f:=:int:target_region_ok_for_watchpoint:CORE_ADDR addr, int len:addr, len
  F:=:int:address_class_type_flags:int byte_size, int 
dwarf2_addr_class:byte_size, dwarf2_addr_class
  M::const char *:address_class_type_flags_to_name:int type_flags:type_flags
  M::int:address_class_name_to_type_flags:const char *name, int 
*type_flags_ptr:name, type_flags_ptr


-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Orjan Friberg]

Orjan Friberg wrote:
> 
> Could something as straightforward as this be the answer?  (gdbarch.[hc] 
> diffs not included.)

Apologies for the botched ChangeLog entry; this is what it was meant to look like:

2005-01-25  Orjan Friberg  <orjanf@axis.com>

	* gdbarch.sh (target_has_hardware_watchpoints)
	(target_can_use_hardware_watchpoint, target_region_ok_for_watchpoint):
	Add.
	* gdbarch.h: Re-generate.
	* gdbarch.c: Ditto.

-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Daniel Jacobowitz]

On Tue, Jan 25, 2005 at 03:44:48PM +0100, Orjan Friberg wrote:
> Orjan Friberg wrote:
> >
> >Could something as straightforward as this be the answer?  (gdbarch.[hc] 
> >diffs not included.)
> 
> Apologies for the botched ChangeLog entry; this is what it was meant to 
> look like:
> 
> 2005-01-25  Orjan Friberg  <orjanf@axis.com>
> 
> 	* gdbarch.sh (target_has_hardware_watchpoints)
> 	(target_can_use_hardware_watchpoint, 
> 	target_region_ok_for_watchpoint):
> 	Add.
> 	* gdbarch.h: Re-generate.
> 	* gdbarch.c: Ditto.

Those two ChangeLog entries were exactly the same... try again?

-- 
Daniel Jacobowitz

Re: New port: CRISv32

[Orjan Friberg]

Daniel Jacobowitz wrote:
> 
> Those two ChangeLog entries were exactly the same... try again?

The gdbarch.h line was preceded by 8 spaces instead of a tab in the first one 
(my mail client displays them differently).  Or did you mean that both looked wrong?

-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Daniel Jacobowitz]

On Tue, Jan 25, 2005 at 04:02:33PM +0100, Orjan Friberg wrote:
> Daniel Jacobowitz wrote:
> >
> >Those two ChangeLog entries were exactly the same... try again?
> 
> The gdbarch.h line was preceded by 8 spaces instead of a tab in the first 
> one (my mail client displays them differently).  Or did you mean that both 

Ah, I couldn't tell the difference.

> looked wrong?

You've got some comma/parentheses confusion at the end of lines.  I
believe the GDB convention is to always separate multi-line function
lists with close parens.

-- 
Daniel Jacobowitz

Re: New port: CRISv32

[Andrew Cagney]

Orjan Friberg wrote:
> Andrew Cagney wrote:
> 
>> Orjan Friberg wrote:
>>
>>>
>>> 2005-01-15  Orjan Friberg  <orjanf@axis.com>
>>>
>>>     * config/cris/tm-cris.h: Resurrect.
>>>     (TARGET_HAS_HARDWARE_WATCHPOINTS, 
>>> TARGET_CAN_USE_HARDWARE_WATCHPOINT)
>>>     (TARGET_REGION_OK_FOR_HW_WATCHPOINT): Define.
> 
> 
> [snip]
> 
>> We're going to need to figure out how to fix things so that these 
>> macros are avoided.
> 
> 
> Could something as straightforward as this be the answer?  (gdbarch.[hc] 
> diffs not included.)
> 
> 2005-01-25  Orjan Friberg  <orjanf@axis.com>
> 
>     * gdbarch.sh (target_has_hardware_watchpoints)
>     (target_can_use_hardware_watchpoint, target_region_ok_for_watchpoint):
>     Add.
>         * gdbarch.h: Re-generate.
>     * gdbarch.c: Ditto.

It's unfortunatly more complicated than that :-(

The interaction can be drawn as either:

     <gdb>                 <target>              <arch>
       |
       +-target*watchpoint()->.
                              |
                              +--arch*watchpoint()->.
                                                    |
                              .<--target*register()-+

or:

     <gdb>                <target>              <arch>
       |
       +------------arch*watchpoint()------------>.
                                                  |
                             <--target*register()-+

That is either:

- the watchpoint code calls on the target to set up watchpoints
- the target in turn calls on the architecture code to manipulate the 
target setting up the watchpoint

or:

- the watchpoint code calls the architecture code to set up watchpoints
- the arch code in turn manipulates the target code.

Our current implementation is a confused hybrid of both, sigh!

Fixing this is going to involve re-aranging a few deckchairs, and the 
result certainly won't directly mesh with your current code :-(

Until this is done can you commit the new code, but minus the tm-*.h 
file (i.e., minus watchpoints).

Andrew

> Index: gdbarch.sh
> ===================================================================
> RCS file: /cvs/src/src/gdb/gdbarch.sh,v
> retrieving revision 1.352
> diff -u -r1.352 gdbarch.sh
> --- gdbarch.sh  3 Dec 2004 23:59:52 -0000       1.352
> +++ gdbarch.sh  25 Jan 2005 14:25:33 -0000
> @@ -650,7 +650,10 @@
>  f:=:void:coff_make_msymbol_special:int val, struct minimal_symbol 
> *msym:val, msym::default_coff_make_msymbol_special::0
>  v:=:const char *:name_of_malloc:::"malloc":"malloc"::0:NAME_OF_MALLOC
>  v:=:int:cannot_step_breakpoint:::0:0::0
> +v:=:int:target_has_hardware_watchpoints:::0:0::0
>  v:=:int:have_nonsteppable_watchpoint:::0:0::0
> +f:=:int:target_can_use_hardware_watchpoint:int type, int count, int 
> other:type, count, other
> +f:=:int:target_region_ok_for_watchpoint:CORE_ADDR addr, int len:addr, len
>  F:=:int:address_class_type_flags:int byte_size, int 
> dwarf2_addr_class:byte_size, dwarf2_addr_class
>  M::const char *:address_class_type_flags_to_name:int type_flags:type_flags
>  M::int:address_class_name_to_type_flags:const char *name, int 
> *type_flags_ptr:name, type_flags_ptr
> 
> 

Re: New port: CRISv32

[Orjan Friberg]

Daniel Jacobowitz wrote:
> On Tue, Jan 25, 2005 at 03:44:48PM +0100, Orjan Friberg wrote:
> 
>>Orjan Friberg wrote:
>>
>>2005-01-25  Orjan Friberg  <orjanf@axis.com>
>>
>>	* gdbarch.sh (target_has_hardware_watchpoints)
>>	(target_can_use_hardware_watchpoint, 
>>	target_region_ok_for_watchpoint):

You sure it's not your mail client wrapping the text around to fit your window 
width ;) ?  Either that, or my Mozilla mail settings are wrong.  When I look at 
either of the last two ChangeLog entries I posted they look ok*; ditto if I 
"reply" and get the "> " inserted at the beginning of each line.

* ok meaning that target_can_use_hardware_watchpoint and 
target_region_ok_for_watchpoint are indeed on the same line in the ChangeLog entry.

-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Orjan Friberg]

Andrew Cagney wrote:
> 
> Until this is done can you commit the new code, but minus the tm-*.h 
> file (i.e., minus watchpoints).

Does that mean it's ok to leave the various watchpoint-related functions in the 
tdep file?  (That way I can keep the tm file locally for watchpoint support, and 
still easily diff against the repository for other changes that I do.)

-- 
Orjan Friberg
Axis Communications

Re: New port: CRISv32

[Andrew Cagney]

Orjan Friberg wrote:
> Andrew Cagney wrote:
> 
>>
>> Until this is done can you commit the new code, but minus the tm-*.h 
>> file (i.e., minus watchpoints).
> 
> 
> Does that mean it's ok to leave the various watchpoint-related functions 
> in the tdep file?  (That way I can keep the tm file locally for 
> watchpoint support, and still easily diff against the repository for 
> other changes that I do.)

Yes, definitly.

Andrew

Re: New port: CRISv32

[Daniel Jacobowitz]

On Tue, Jan 25, 2005 at 05:20:04PM +0100, Orjan Friberg wrote:
> Daniel Jacobowitz wrote:
> >On Tue, Jan 25, 2005 at 03:44:48PM +0100, Orjan Friberg wrote:
> >
> >>Orjan Friberg wrote:
> >>
> >>2005-01-25  Orjan Friberg  <orjanf@axis.com>
> >>
> >>	* gdbarch.sh (target_has_hardware_watchpoints)
> >>	(target_can_use_hardware_watchpoint, 
> >>	target_region_ok_for_watchpoint):
> 
> You sure it's not your mail client wrapping the text around to fit your 
> window width ;) ?  Either that, or my Mozilla mail settings are wrong.  
> When I look at either of the last two ChangeLog entries I posted they look 
> ok*; ditto if I "reply" and get the "> " inserted at the beginning of each 
> line.
> 
> * ok meaning that target_can_use_hardware_watchpoint and 
> target_region_ok_for_watchpoint are indeed on the same line in the 
> ChangeLog entry.

They are definitely on different lines here.  Mozilla must be flowing
text for you.  Oh well, let's not worry about it.

-- 
Daniel Jacobowitz

Re: New port: CRISv32

[Orjan Friberg]

Andrew Cagney wrote:
> Orjan Friberg wrote:
>>
>> Does that mean it's ok to leave the various watchpoint-related 
>> functions in the tdep file?  (That way I can keep the tm file locally 
>> for watchpoint support, and still easily diff against the repository 
>> for other changes that I do.)
> 
> 
> Yes, definitly.

Ok, committed.

-- 
Orjan Friberg
Axis Communications