Re: Unreviewed patches

[Kazu Hirata <kazu@cs.umass.edu>]

Hi Michael,

> Yes, thanks.  My problem is this: your patch uses a host-order
> sign-extend to simulate a target-order sign-extend.  If the host
> and target have different byte orders, you lose.  That's probably
> why the simulator uses breg[] to fetch bytes, instead of using
> wreg and masking.
> 
> I suggest that it would be comparatively easy to extend the
> breg[] array so that it would cover at least the first three
> bytes in the register (and possibly all four, just because
> it's no extra effort).  Something like the attached.
> 
> Then the code that references breg[] does not need to change.

I understand your concern.  But then if GET_W_REG may give a
byte-swapped value, would the following be endian unsafe?

	case O (O_ADD, SW):
	  rd = GET_W_REG (code->dst.reg);
	  ea = fetch (&code->src);
	  res = rd + ea;
	  goto alu16;

The addition is done in host-order.

Kazu Hirata