[PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

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This is the second of two patches to get aarch64 ILP32 support into
gdb.  The first patch was a couple of bfd files, this patch is the gdb
and gdbserver changes.  This is an update of the patches that Andrew
Pinski submitted here:

	https://sourceware.org/ml/binutils/2016-09/msg00004.html

This patch includes everything from his patch 2 and 3.  I updated the
patches to top-of-tree, addressed the comments that were made at the
time, and retested with the binutils and gdb testsuites.

Steve Ellcey
sellcey@cavium.com


gdb ChangeLog:

2017-01-24  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>

	* aarch64-tdep.h (gdbarch_tdep) <ilp32>: New field.
	* aarch64-tdep.c: Include "features/aarch64_ilp32.c".
	(aarch64_gdbarch_init): Setup ILP32 support.
	Make sure the gdbarches have compatible ilp32 flags.
	Set long and ptr sizes correctly for ilp32.
	(_initialize_aarch64_tdep): Call initialize_tdesc_aarch64_ilp32.
	* aarch64-linux-tdep.c (aarch64_linux_init_abi):
	Add support for ILP32.
	* features/Makefile (WHICH): Add aarch64_ilp32.
	(aarch64_ilp32-expedite): Set.
	(XMLTOC): Add aarch64_ilp32.xml.
	* features/aarch64_ilp32-core.xml: New file.
	* features/aarch64_ilp32.xml: New file.
	* features/aarch64_ilp32.c: Generate.
	* regformats/aarch64_ilp32.dat: Generate.

gdb/gdbserver ChangeLog:

2017-01-24  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>

	* Makefile.in (clean): Remove aarch64_ilp32.c also.
	(aarch64_ilp32-ipa.o): New target.
	(aarch64_ilp32.c): New target.
	* configure.srv (aarch64*-*-linux*): Add ilp32 files
	to srv_regobj, srv_xmlfiles and ipa_obj.
	* linux-aarch64-ipa.c (init_registers_aarch64_ilp32):
	Declare.
	(tdesc_aarch64_ilp32): Likewise.
	(get_ipa_tdesc): Return tdesc_aarch64_ilp32 for ILP32.
	(initialize_low_tracepoint): Call init_registers_aarch64_ilp32
	for ILP32.
	* linux-aarch64-low.c (init_registers_aarch64_ilp32): Declare.
	(tdesc_aarch64_ilp32): Likewise.
	(aarch64_linux_read_description): Return tdesc_aarch64_ilp32
	for ILP32 executables.
	(initialize_low_arch): Call init_registers_aarch64_ilp32.

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diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index b94ccb2..6d0c3bd 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -1000,8 +1000,12 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 
   linux_init_abi (info, gdbarch);
 
-  set_solib_svr4_fetch_link_map_offsets (gdbarch,
-					 svr4_lp64_fetch_link_map_offsets);
+  if (tdep->ilp32)
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_ilp32_fetch_link_map_offsets);
+  else
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_lp64_fetch_link_map_offsets);
 
   /* Enable TLS support.  */
   set_gdbarch_fetch_tls_load_module_address (gdbarch,
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 801c03d..6019dea 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -57,6 +57,7 @@
 #include "record-full.h"
 
 #include "features/aarch64.c"
+#include "features/aarch64_ilp32.c"
 
 #include "arch/aarch64-insn.h"
 
@@ -2851,10 +2852,14 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   const struct tdesc_feature *feature;
   int num_regs = 0;
   int num_pseudo_regs = 0;
+  int ilp32 = FALSE;
+
+  if (info.bfd_arch_info->mach == bfd_mach_aarch64_ilp32)
+    ilp32 = TRUE;
 
   /* Ensure we always have a target descriptor.  */
   if (!tdesc_has_registers (tdesc))
-    tdesc = tdesc_aarch64;
+    tdesc = ilp32 ? tdesc_aarch64_ilp32 : tdesc_aarch64;
 
   gdb_assert (tdesc);
 
@@ -2908,6 +2913,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
        best_arch != NULL;
        best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
     {
+      /* ILP32 and LP64 are incompatible. */
+      if (gdbarch_tdep (arches->gdbarch)->ilp32 != ilp32)
+	continue;
       /* Found a match.  */
       break;
     }
@@ -2926,6 +2934,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   tdep->lowest_pc = 0x20;
   tdep->jb_pc = -1;		/* Longjump support not enabled by default.  */
   tdep->jb_elt_size = 8;
+  tdep->ilp32 = ilp32;
 
   set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
   set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
@@ -2968,9 +2977,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   set_gdbarch_float_bit (gdbarch, 32);
   set_gdbarch_double_bit (gdbarch, 64);
   set_gdbarch_long_double_bit (gdbarch, 128);
-  set_gdbarch_long_bit (gdbarch, 64);
+  set_gdbarch_long_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_long_long_bit (gdbarch, 64);
-  set_gdbarch_ptr_bit (gdbarch, 64);
+  set_gdbarch_ptr_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_char_signed (gdbarch, 0);
   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
@@ -3043,6 +3052,7 @@ _initialize_aarch64_tdep (void)
 		    aarch64_dump_tdep);
 
   initialize_tdesc_aarch64 ();
+  initialize_tdesc_aarch64_ilp32 ();
 
   /* Debug this file's internals.  */
   add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 85c6a97..4c9b58d 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -97,6 +97,9 @@ struct gdbarch_tdep
 
   /* syscall record.  */
   int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
+  /* If this is ILP32 or LP64.  */
+  int ilp32;
+
 };
 
 extern struct target_desc *tdesc_aarch64;
diff --git a/gdb/features/Makefile b/gdb/features/Makefile
index 63f8248..89d57c4 100644
--- a/gdb/features/Makefile
+++ b/gdb/features/Makefile
@@ -43,7 +43,7 @@
 #
 #   make GDB=/path/to/gdb XMLTOC="xml files" cfiles
 
-WHICH = aarch64 \
+WHICH = aarch64 aarch64_ilp32 \
 	arm/arm-with-iwmmxt arm/arm-with-vfpv2 arm/arm-with-vfpv3 \
 	arm/arm-with-neon \
 	i386/i386 i386/i386-linux \
@@ -81,6 +81,7 @@ WHICH = aarch64 \
 
 # Record which registers should be sent to GDB by default after stop.
 aarch64-expedite = x29,sp,pc
+aarch64_ilp32-expedite = x29,sp,pc
 arm-expedite = r11,sp,pc
 i386-expedite = ebp,esp,eip
 amd64-expedite = rbp,rsp,rip
@@ -127,6 +128,7 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
 # to make on the command line.
 XMLTOC = \
 	aarch64.xml \
+	aarch64_ilp32.xml \
 	arc-v2.xml \
 	arc-arcompact.xml \
 	arm/arm-with-iwmmxt.xml \
diff --git a/gdb/features/aarch64_ilp32-core.xml b/gdb/features/aarch64_ilp32-core.xml
index e69de29..ace8d62 100644
--- a/gdb/features/aarch64_ilp32-core.xml
+++ b/gdb/features/aarch64_ilp32-core.xml
@@ -0,0 +1,67 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
+     Contributed by ARM Ltd.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.core">
+  <reg name="x0" bitsize="64"/>
+  <reg name="x1" bitsize="64"/>
+  <reg name="x2" bitsize="64"/>
+  <reg name="x3" bitsize="64"/>
+  <reg name="x4" bitsize="64"/>
+  <reg name="x5" bitsize="64"/>
+  <reg name="x6" bitsize="64"/>
+  <reg name="x7" bitsize="64"/>
+  <reg name="x8" bitsize="64"/>
+  <reg name="x9" bitsize="64"/>
+  <reg name="x10" bitsize="64"/>
+  <reg name="x11" bitsize="64"/>
+  <reg name="x12" bitsize="64"/>
+  <reg name="x13" bitsize="64"/>
+  <reg name="x14" bitsize="64"/>
+  <reg name="x15" bitsize="64"/>
+  <reg name="x16" bitsize="64"/>
+  <reg name="x17" bitsize="64"/>
+  <reg name="x18" bitsize="64"/>
+  <reg name="x19" bitsize="64"/>
+  <reg name="x20" bitsize="64"/>
+  <reg name="x21" bitsize="64"/>
+  <reg name="x22" bitsize="64"/>
+  <reg name="x23" bitsize="64"/>
+  <reg name="x24" bitsize="64"/>
+  <reg name="x25" bitsize="64"/>
+  <reg name="x26" bitsize="64"/>
+  <reg name="x27" bitsize="64"/>
+  <reg name="x28" bitsize="64"/>
+  <reg name="x29" bitsize="64"/>
+  <reg name="x30" bitsize="64"/>
+  <reg name="sp" bitsize="64" type="int64"/>
+
+  <reg name="pc" bitsize="64" type="uint64"/>
+
+  <flags id="cpsr_flags" size="4">
+    <field name="SP" start="0" type="bool"/>
+    <field name="" start="1" end="1"/>
+    <field name="EL" start="2" end="3"/>
+    <field name="nRW" start="4" type="bool"/>
+    <field name="" start="5" end="5"/>
+    <field name="F" start="6" type="bool"/>
+    <field name="I" start="7" type="bool"/>
+    <field name="A" start="8" type="bool"/>
+    <field name="D" start="9" type="bool"/>
+
+    <field name="IL" start="20" type="bool"/>
+    <field name="SS" start="21" type="bool"/>
+
+    <field name="V" start="28" type="bool"/>
+    <field name="C" start="29" type="bool"/>
+    <field name="Z" start="30" type="bool"/>
+    <field name="N" start="31" type="bool"/>
+  </flags>
+  <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
+
+</feature>
diff --git a/gdb/features/aarch64_ilp32.c b/gdb/features/aarch64_ilp32.c
index e69de29..2195130 100644
--- a/gdb/features/aarch64_ilp32.c
+++ b/gdb/features/aarch64_ilp32.c
@@ -0,0 +1,191 @@
+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
+  Original: aarch64_ilp32.xml */
+
+#include "defs.h"
+#include "osabi.h"
+#include "target-descriptions.h"
+
+struct target_desc *tdesc_aarch64_ilp32;
+static void
+initialize_tdesc_aarch64_ilp32 (void)
+{
+  struct target_desc *result = allocate_target_description ();
+  struct tdesc_feature *feature;
+  struct tdesc_type *field_type;
+  struct tdesc_type *type;
+
+  set_tdesc_architecture (result, bfd_scan_arch ("aarch64:ilp32"));
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.core");
+  type = tdesc_create_flags (feature, "cpsr_flags", 4);
+  tdesc_add_flag (type, 0, "SP");
+  tdesc_add_bitfield (type, "", 1, 1);
+  tdesc_add_bitfield (type, "EL", 2, 3);
+  tdesc_add_flag (type, 4, "nRW");
+  tdesc_add_bitfield (type, "", 5, 5);
+  tdesc_add_flag (type, 6, "F");
+  tdesc_add_flag (type, 7, "I");
+  tdesc_add_flag (type, 8, "A");
+  tdesc_add_flag (type, 9, "D");
+  tdesc_add_flag (type, 20, "IL");
+  tdesc_add_flag (type, 21, "SS");
+  tdesc_add_flag (type, 28, "V");
+  tdesc_add_flag (type, 29, "C");
+  tdesc_add_flag (type, 30, "Z");
+  tdesc_add_flag (type, 31, "N");
+
+  tdesc_create_reg (feature, "x0", 0, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x1", 1, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x2", 2, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x3", 3, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x4", 4, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x5", 5, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x6", 6, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x7", 7, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x8", 8, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x9", 9, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x10", 10, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x11", 11, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x12", 12, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x13", 13, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x14", 14, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x15", 15, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x16", 16, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x17", 17, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x18", 18, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x19", 19, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x20", 20, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x21", 21, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x22", 22, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x23", 23, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x24", 24, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x25", 25, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x26", 26, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x27", 27, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x28", 28, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x29", 29, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "x30", 30, 1, NULL, 64, "int");
+  tdesc_create_reg (feature, "sp", 31, 1, NULL, 64, "int64");
+  tdesc_create_reg (feature, "pc", 32, 1, NULL, 64, "uint64");
+  tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "cpsr_flags");
+
+  feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.fpu");
+  field_type = tdesc_named_type (feature, "ieee_double");
+  tdesc_create_vector (feature, "v2d", field_type, 2);
+
+  field_type = tdesc_named_type (feature, "uint64");
+  tdesc_create_vector (feature, "v2u", field_type, 2);
+
+  field_type = tdesc_named_type (feature, "int64");
+  tdesc_create_vector (feature, "v2i", field_type, 2);
+
+  field_type = tdesc_named_type (feature, "ieee_single");
+  tdesc_create_vector (feature, "v4f", field_type, 4);
+
+  field_type = tdesc_named_type (feature, "uint32");
+  tdesc_create_vector (feature, "v4u", field_type, 4);
+
+  field_type = tdesc_named_type (feature, "int32");
+  tdesc_create_vector (feature, "v4i", field_type, 4);
+
+  field_type = tdesc_named_type (feature, "uint16");
+  tdesc_create_vector (feature, "v8u", field_type, 8);
+
+  field_type = tdesc_named_type (feature, "int16");
+  tdesc_create_vector (feature, "v8i", field_type, 8);
+
+  field_type = tdesc_named_type (feature, "uint8");
+  tdesc_create_vector (feature, "v16u", field_type, 16);
+
+  field_type = tdesc_named_type (feature, "int8");
+  tdesc_create_vector (feature, "v16i", field_type, 16);
+
+  field_type = tdesc_named_type (feature, "uint128");
+  tdesc_create_vector (feature, "v1u", field_type, 1);
+
+  field_type = tdesc_named_type (feature, "int128");
+  tdesc_create_vector (feature, "v1i", field_type, 1);
+
+  type = tdesc_create_union (feature, "vnd");
+  field_type = tdesc_named_type (feature, "v2d");
+  tdesc_add_field (type, "f", field_type);
+  field_type = tdesc_named_type (feature, "v2u");
+  tdesc_add_field (type, "u", field_type);
+  field_type = tdesc_named_type (feature, "v2i");
+  tdesc_add_field (type, "s", field_type);
+
+  type = tdesc_create_union (feature, "vns");
+  field_type = tdesc_named_type (feature, "v4f");
+  tdesc_add_field (type, "f", field_type);
+  field_type = tdesc_named_type (feature, "v4u");
+  tdesc_add_field (type, "u", field_type);
+  field_type = tdesc_named_type (feature, "v4i");
+  tdesc_add_field (type, "s", field_type);
+
+  type = tdesc_create_union (feature, "vnh");
+  field_type = tdesc_named_type (feature, "v8u");
+  tdesc_add_field (type, "u", field_type);
+  field_type = tdesc_named_type (feature, "v8i");
+  tdesc_add_field (type, "s", field_type);
+
+  type = tdesc_create_union (feature, "vnb");
+  field_type = tdesc_named_type (feature, "v16u");
+  tdesc_add_field (type, "u", field_type);
+  field_type = tdesc_named_type (feature, "v16i");
+  tdesc_add_field (type, "s", field_type);
+
+  type = tdesc_create_union (feature, "vnq");
+  field_type = tdesc_named_type (feature, "v1u");
+  tdesc_add_field (type, "u", field_type);
+  field_type = tdesc_named_type (feature, "v1i");
+  tdesc_add_field (type, "s", field_type);
+
+  type = tdesc_create_union (feature, "aarch64v");
+  field_type = tdesc_named_type (feature, "vnd");
+  tdesc_add_field (type, "d", field_type);
+  field_type = tdesc_named_type (feature, "vns");
+  tdesc_add_field (type, "s", field_type);
+  field_type = tdesc_named_type (feature, "vnh");
+  tdesc_add_field (type, "h", field_type);
+  field_type = tdesc_named_type (feature, "vnb");
+  tdesc_add_field (type, "b", field_type);
+  field_type = tdesc_named_type (feature, "vnq");
+  tdesc_add_field (type, "q", field_type);
+
+  tdesc_create_reg (feature, "v0", 34, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v1", 35, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v2", 36, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v3", 37, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v4", 38, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v5", 39, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v6", 40, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v7", 41, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v8", 42, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v9", 43, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v10", 44, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v11", 45, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v12", 46, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v13", 47, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v14", 48, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v15", 49, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v16", 50, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v17", 51, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v18", 52, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v19", 53, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v20", 54, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v21", 55, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v22", 56, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v23", 57, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v24", 58, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v25", 59, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v26", 60, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v27", 61, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v28", 62, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v29", 63, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v30", 64, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "v31", 65, 1, NULL, 128, "aarch64v");
+  tdesc_create_reg (feature, "fpsr", 66, 1, NULL, 32, "int");
+  tdesc_create_reg (feature, "fpcr", 67, 1, NULL, 32, "int");
+
+  tdesc_aarch64_ilp32 = result;
+}
diff --git a/gdb/features/aarch64_ilp32.xml b/gdb/features/aarch64_ilp32.xml
index e69de29..9c9b23a 100644
--- a/gdb/features/aarch64_ilp32.xml
+++ b/gdb/features/aarch64_ilp32.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
+     Contributed by ARM Ltd.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>aarch64:ilp32</architecture>
+  <xi:include href="aarch64_ilp32-core.xml"/>
+  <xi:include href="aarch64-fpu.xml"/>
+</target>
diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
index 75736b6..42433a6 100644
--- a/gdb/gdbserver/Makefile.in
+++ b/gdb/gdbserver/Makefile.in
@@ -419,6 +419,7 @@ clean:
 	rm -f gdbserver$(EXEEXT) gdbreplay$(EXEEXT) core make.log
 	rm -f $(IPA_LIB)
 	rm -f aarch64.c
+	rm -f aarch64_ilp32.c
 	rm -f reg-arm.c reg-bfin.c i386.c reg-ia64.c reg-m32r.c reg-m68k.c
 	rm -f reg-sh.c reg-sparc.c reg-spu.c amd64.c i386-linux.c
 	rm -f reg-cris.c reg-crisv32.c amd64-linux.c reg-xtensa.c
@@ -607,6 +608,9 @@ linux-aarch64-ipa.o: linux-aarch64-ipa.c
 aarch64-ipa.o: aarch64.c
 	$(IPAGENT_COMPILE) $<
 	$(POSTCOMPILE)
+aarch64_ilp32-ipa.o: aarch64_ilp32.c
+	$(IPAGENT_COMPILE) $<
+	$(POSTCOMPILE)
 linux-s390-ipa.o: linux-s390-ipa.c
 	$(IPAGENT_COMPILE) $<
 	$(POSTCOMPILE)
@@ -870,6 +874,8 @@ aarch64-insn.o: ../arch/aarch64-insn.c
 
 aarch64.c : $(srcdir)/../regformats/aarch64.dat $(regdat_sh)
 	$(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64.dat aarch64.c
+aarch64_ilp32.c : $(srcdir)/../regformats/aarch64_ilp32.dat $(regdat_sh)
+	$(SHELL) $(regdat_sh) $(srcdir)/../regformats/aarch64_ilp32.dat aarch64_ilp32.c
 reg-arm.c : $(srcdir)/../regformats/reg-arm.dat $(regdat_sh)
 	$(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-arm.dat reg-arm.c
 arm-with-iwmmxt.c : $(srcdir)/../regformats/arm/arm-with-iwmmxt.dat $(regdat_sh)
diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
index 3267599..8b49f25 100644
--- a/gdb/gdbserver/configure.srv
+++ b/gdb/gdbserver/configure.srv
@@ -50,7 +50,7 @@ srv_linux_obj="linux-low.o linux-osdata.o linux-procfs.o linux-ptrace.o linux-wa
 
 case "${target}" in
   aarch64*-*-linux*)
-			srv_regobj="aarch64.o"
+			srv_regobj="aarch64.o aarch64_ilp32.o"
 			srv_regobj="${srv_regobj} arm-with-neon.o"
 			srv_tgtobj="linux-aarch64-low.o aarch64-linux-hw-point.o"
 			srv_tgtobj="$srv_tgtobj linux-aarch32-low.o"
@@ -58,14 +58,16 @@ case "${target}" in
 			srv_tgtobj="$srv_tgtobj aarch64-linux.o"
 			srv_tgtobj="$srv_tgtobj aarch64-insn.o"
 			srv_tgtobj="${srv_tgtobj} $srv_linux_obj"
-			srv_xmlfiles="aarch64.xml"
+			srv_xmlfiles="aarch64.xml aarch64_ilp32.xml"
 			srv_xmlfiles="${srv_xmlfiles} aarch64-core.xml"
+			srv_xmlfiles="${srv_xmlfiles} aarch64_ilp32-core.xml"
 			srv_xmlfiles="${srv_xmlfiles} aarch64-fpu.xml"
 			srv_xmlfiles="${srv_xmlfiles} arm/arm-core.xml arm/arm-vfpv3.xml"
 			srv_xmlfiles="${srv_xmlfiles} arm/arm-with-neon.xml"
 			srv_linux_regsets=yes
 			srv_linux_thread_db=yes
-			ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o"
+			ipa_obj="linux-aarch64-ipa.o aarch64-ipa.o aarch64_ilp32
+-ipa.o"
 			;;
   arm*-*-linux*)	srv_regobj="reg-arm.o arm-with-iwmmxt.o"
 			srv_regobj="${srv_regobj} arm-with-vfpv2.o"
diff --git a/gdb/gdbserver/linux-aarch64-ipa.c b/gdb/gdbserver/linux-aarch64-ipa.c
index ad10590..8c43880 100644
--- a/gdb/gdbserver/linux-aarch64-ipa.c
+++ b/gdb/gdbserver/linux-aarch64-ipa.c
@@ -29,6 +29,9 @@
 /* Defined in auto-generated file aarch64.c.  */
 void init_registers_aarch64 (void);
 extern const struct target_desc *tdesc_aarch64;
+/* Defined in auto-generated file aarch64_ilp32.c.  */
+void init_registers_aarch64_ilp32 (void);
+extern const struct target_desc *tdesc_aarch64_ilp32;
 
 /* Each register saved by the jump pad is in a 16 byte cell.  */
 #define FT_CR_SIZE 16
@@ -155,6 +158,9 @@ get_raw_reg (const unsigned char *raw_regs, int regnum)
 const struct target_desc *
 get_ipa_tdesc (int idx)
 {
+  if (sizeof (void *) == 4)
+    return tdesc_aarch64_ilp32;
+
   return tdesc_aarch64;
 }
 
@@ -207,5 +213,8 @@ alloc_jump_pad_buffer (size_t size)
 void
 initialize_low_tracepoint (void)
 {
-  init_registers_aarch64 ();
+  if (sizeof (void *) == 4)
+    init_registers_aarch64_ilp32 ();
+  else
+    init_registers_aarch64 ();
 }
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index 334310b..7258c83 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -42,6 +42,8 @@
 /* Defined in auto-generated files.  */
 void init_registers_aarch64 (void);
 extern const struct target_desc *tdesc_aarch64;
+void init_registers_aarch64_ilp32 (void);
+extern const struct target_desc *tdesc_aarch64_ilp32;
 
 #ifdef HAVE_SYS_REG_H
 #include <sys/reg.h>
@@ -484,8 +486,13 @@ aarch64_linux_read_description (void)
 
   is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
 
-  if (is_elf64)
+  if (sizeof (void *) == 4 && is_elf64)
+    error (_("Can't debug 64-bit process with 32-bit GDBserver"));
+
+  if (machine == EM_AARCH64 && is_elf64)
     return tdesc_aarch64;
+  else if (machine == EM_AARCH64 && !is_elf64)
+    return tdesc_aarch64_ilp32;
   else
     return tdesc_arm_with_neon;
 }
@@ -3009,6 +3016,7 @@ void
 initialize_low_arch (void)
 {
   init_registers_aarch64 ();
+  init_registers_aarch64_ilp32 ();
 
   initialize_low_arch_aarch32 ();
 
diff --git a/gdb/regformats/aarch64_ilp32.dat b/gdb/regformats/aarch64_ilp32.dat
index e69de29..bcef3e1 100644
--- a/gdb/regformats/aarch64_ilp32.dat
+++ b/gdb/regformats/aarch64_ilp32.dat
@@ -0,0 +1,73 @@
+# THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi :set ro:
+# Generated from: aarch64_ilp32.xml
+name:aarch64_ilp32
+xmltarget:aarch64_ilp32.xml
+expedite:x29,sp,pc
+64:x0
+64:x1
+64:x2
+64:x3
+64:x4
+64:x5
+64:x6
+64:x7
+64:x8
+64:x9
+64:x10
+64:x11
+64:x12
+64:x13
+64:x14
+64:x15
+64:x16
+64:x17
+64:x18
+64:x19
+64:x20
+64:x21
+64:x22
+64:x23
+64:x24
+64:x25
+64:x26
+64:x27
+64:x28
+64:x29
+64:x30
+64:sp
+64:pc
+32:cpsr
+128:v0
+128:v1
+128:v2
+128:v3
+128:v4
+128:v5
+128:v6
+128:v7
+128:v8
+128:v9
+128:v10
+128:v11
+128:v12
+128:v13
+128:v14
+128:v15
+128:v16
+128:v17
+128:v18
+128:v19
+128:v20
+128:v21
+128:v22
+128:v23
+128:v24
+128:v25
+128:v26
+128:v27
+128:v28
+128:v29
+128:v30
+128:v31
+32:fpsr
+32:fpcr

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On 17-01-24 16:20:39, Steve Ellcey wrote:
> @@ -2851,10 +2852,14 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
>    const struct tdesc_feature *feature;
>    int num_regs = 0;
>    int num_pseudo_regs = 0;
> +  int ilp32 = FALSE;
> +

We can use bool now, because we moved to C++ :)

> +  if (info.bfd_arch_info->mach == bfd_mach_aarch64_ilp32)
> +    ilp32 = TRUE;
>  
>    /* Ensure we always have a target descriptor.  */
>    if (!tdesc_has_registers (tdesc))
> -    tdesc = tdesc_aarch64;
> +    tdesc = ilp32 ? tdesc_aarch64_ilp32 : tdesc_aarch64;
>  
>    gdb_assert (tdesc);
>  
> diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
> index 85c6a97..4c9b58d 100644
> --- a/gdb/aarch64-tdep.h
> +++ b/gdb/aarch64-tdep.h
> @@ -97,6 +97,9 @@ struct gdbarch_tdep
>  
>    /* syscall record.  */
>    int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
> +  /* If this is ILP32 or LP64.  */
> +  int ilp32;

bool ilp32;

> diff --git a/gdb/features/aarch64_ilp32-core.xml b/gdb/features/aarch64_ilp32-core.xml
> index e69de29..ace8d62 100644
> --- a/gdb/features/aarch64_ilp32-core.xml
> +++ b/gdb/features/aarch64_ilp32-core.xml
> @@ -0,0 +1,67 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.

2016 - 2017

> +     Contributed by ARM Ltd.

Remove this line according to the attribution policy
https://sourceware.org/gdb/wiki/ContributionChecklist#Attribution

> +
> +     Copying and distribution of this file, with or without modification,
> +     are permitted in any medium without royalty provided the copyright
> +     notice and this notice are preserved.  -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.aarch64.core">
> +  <reg name="x0" bitsize="64"/>
> +  <reg name="x1" bitsize="64"/>
> +  <reg name="x2" bitsize="64"/>
> +  <reg name="x3" bitsize="64"/>
> +  <reg name="x4" bitsize="64"/>
> +  <reg name="x5" bitsize="64"/>
> +  <reg name="x6" bitsize="64"/>
> +  <reg name="x7" bitsize="64"/>
> +  <reg name="x8" bitsize="64"/>
> +  <reg name="x9" bitsize="64"/>
> +  <reg name="x10" bitsize="64"/>
> +  <reg name="x11" bitsize="64"/>
> +  <reg name="x12" bitsize="64"/>
> +  <reg name="x13" bitsize="64"/>
> +  <reg name="x14" bitsize="64"/>
> +  <reg name="x15" bitsize="64"/>
> +  <reg name="x16" bitsize="64"/>
> +  <reg name="x17" bitsize="64"/>
> +  <reg name="x18" bitsize="64"/>
> +  <reg name="x19" bitsize="64"/>
> +  <reg name="x20" bitsize="64"/>
> +  <reg name="x21" bitsize="64"/>
> +  <reg name="x22" bitsize="64"/>
> +  <reg name="x23" bitsize="64"/>
> +  <reg name="x24" bitsize="64"/>
> +  <reg name="x25" bitsize="64"/>
> +  <reg name="x26" bitsize="64"/>
> +  <reg name="x27" bitsize="64"/>
> +  <reg name="x28" bitsize="64"/>
> +  <reg name="x29" bitsize="64"/>
> +  <reg name="x30" bitsize="64"/>

I diff aarch64-core.xml and aarch64_ilp32-core.xml, and see a lot of
differences,

> +  <reg name="sp" bitsize="64" type="int64"/>

s/int64/uint64/ ?

> +
> +  <reg name="pc" bitsize="64" type="uint64"/>

-  <reg name="sp" bitsize="64" type="data_ptr"/>
+  <reg name="sp" bitsize="64" type="int64"/>
 
-  <reg name="pc" bitsize="64" type="code_ptr"/>
+  <reg name="pc" bitsize="64" type="uint64"/>

Do we really need these changes? I know data_ptr and code_ptr is 32-bit
on ilp32, but registers are 64-bit.  However, I still think we shouldn't
create different target descriptions for different ABIs, because target
description is about the hardware stuff.  If we add target descriptions
for different ABIs, we have to add two copies of target descriptions for
two ABIs every time a new hardware feature is added.  That is a pain of
maintenance.

Could you remove these ilp32 xml files, use the existing aarch64 target
description, and try the patch below?

Note that x32 adds xml files some years ago
https://sourceware.org/ml/gdb-patches/2012-04/msg00018.html but I think
the idea is still worth baking and the x32 patch was not fully reviewed.

> +
> +  <flags id="cpsr_flags" size="4">
> +    <field name="SP" start="0" type="bool"/>

-    <field name="SP" start="0" end="0"/>
+    <field name="SP" start="0" type="bool"/>

Why is that? out of sync, maybe?  That may be no longer a question if we
don't need ilp32 target description.

> diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
> index 334310b..7258c83 100644
> --- a/gdb/gdbserver/linux-aarch64-low.c
> +++ b/gdb/gdbserver/linux-aarch64-low.c
> @@ -42,6 +42,8 @@
>  /* Defined in auto-generated files.  */
>  void init_registers_aarch64 (void);
>  extern const struct target_desc *tdesc_aarch64;
> +void init_registers_aarch64_ilp32 (void);
> +extern const struct target_desc *tdesc_aarch64_ilp32;
>  
>  #ifdef HAVE_SYS_REG_H
>  #include <sys/reg.h>
> @@ -484,8 +486,13 @@ aarch64_linux_read_description (void)
>  
>    is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
>  
> -  if (is_elf64)
> +  if (sizeof (void *) == 4 && is_elf64)
> +    error (_("Can't debug 64-bit process with 32-bit GDBserver"));

ilp32 GDBserver can't debug lp64 program?

> +
> +  if (machine == EM_AARCH64 && is_elf64)
>      return tdesc_aarch64;
> +  else if (machine == EM_AARCH64 && !is_elf64)
> +    return tdesc_aarch64_ilp32;
>    else
>      return tdesc_arm_with_neon;

-- 
Yao (齐尧)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 801c03d..e23ac75 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2091,6 +2091,22 @@ aarch64_gen_return_address (struct gdbarch *gdbarch,
 }
 \f
 
+/* Implement the "register_type" gdbarch method.
+   Adjust the register type of $PC and $SP on ILP32.  */
+
+static struct type *
+aarch64_ilp32_register_type (struct gdbarch *gdbarch, int regnum)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  gdb_assert (tdep->ilp32);
+
+  if (regnum == AARCH64_SP_REGNUM || regnum == AARCH64_PC_REGNUM)
+    return builtin_type (gdbarch)->builtin_uint64;
+  else
+    return tdesc_register_type (gdbarch, regnum);
+}
+
 /* Return the pseudo register name corresponding to register regnum.  */
 
 static const char *
@@ -3012,6 +3028,13 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 
   tdesc_use_registers (gdbarch, tdesc, tdesc_data);
 
+  if (ilp32)
+    {
+      /* Override tdesc_register_type to adjust the types of $PC and
+	 $SP in ILP32.  */
+      set_gdbarch_register_type (gdbarch, aarch64_ilp32_register_type);
+    }
+
   /* Add standard register aliases.  */
   for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
     user_reg_add (gdbarch, aarch64_register_aliases[i].name,

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

[-- Attachment #1: Type: text/plain, Size: 2293 bytes --]

On Thu, 2017-01-26 at 14:14 +0000, Yao Qi wrote:
> 
> Could you remove these ilp32 xml files, use the existing aarch64 target
> description, and try the patch below?

Yao,

I removed the ilp32 xml files and applied the patch you included and
made the other changes.  gdb seems to be working as well as it did
with the original patch but I ran into a problem that I missed before.

If I apply the gdb/gdbserver patch attached to this email and the
earlier bfd patch:

	 https://sourceware.org/ml/gdb-patches/2017-01/msg00508.html

and I try to run gdb on an ILP32 program I get:

(gdb) r
Starting program: /home/ubuntu/sellcey/gdb-ilp32/x32 
PC register is not available


I didn't see this before because I didn't have this bfd patch:

	https://sourceware.org/ml/binutils/2016-12/msg00167.html

That patch seems reasonable and it fixed some test failures I had
in the glibc testsuite but it is breaking gdb.  If I undo this
patch by making this change to bfd/cpu-aarch64.c:

 static const bfd_arch_info_type bfd_aarch64_arch_ilp32 =
-  N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, NULL);
+  N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 64, FALSE, NULL);

Then gdb starts working again and I can debug 32 bit programs.

I am not sure how this change to the ILP32 aarch64 bfd description
is affecting gdb and why this change would break things.  Do you
know why this change messes up gdb?

Steve Ellcey
sellcey@cavium.com

2017-01-27  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>
	    Yao Qi  <yao.qi@linaro.org>

	* aarch64-linux-tdep.c (aarch64_linux_init_abi): Set link
	map offsets to 32 or 64 bits.
	* aarch64-tdep.c (aarch64_ilp32_register_type): New function.
	(aarch64_gdbarch_init): Setup ILP32 support.
	Make sure the gdbarches have compatible ilp32 flags.
	Set long and ptr sizes correctly for ilp32.
	* aarch64-tdep.h (gdbarch_tdep) <ilp32>: New field.

2017-01-27  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>

	* linux-aarch64-low.c (aarch64_linux_read_description): Use
	machine instead of is_elf64 to determine architecture.  Give an
	error when using 32 bit gdbserver on 64 bit program.

[-- Attachment #2: gdb-new.patch --]
[-- Type: text/x-patch, Size: 4803 bytes --]

diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index b94ccb2..6d0c3bd 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -1000,8 +1000,12 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 
   linux_init_abi (info, gdbarch);
 
-  set_solib_svr4_fetch_link_map_offsets (gdbarch,
-					 svr4_lp64_fetch_link_map_offsets);
+  if (tdep->ilp32)
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_ilp32_fetch_link_map_offsets);
+  else
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_lp64_fetch_link_map_offsets);
 
   /* Enable TLS support.  */
   set_gdbarch_fetch_tls_load_module_address (gdbarch,
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 801c03d..bc6b0be 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2091,6 +2091,22 @@ aarch64_gen_return_address (struct gdbarch *gdbarch,
 }
 \f
 
+/* Implement the "register_type" gdbarch method.
+   Adjust the register type of $PC and $SP on ILP32.  */
+
+static struct type *
+aarch64_ilp32_register_type (struct gdbarch *gdbarch, int regnum)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  gdb_assert (tdep->ilp32);
+
+  if (regnum == AARCH64_SP_REGNUM || regnum == AARCH64_PC_REGNUM)
+    return builtin_type (gdbarch)->builtin_uint64;
+  else
+    return tdesc_register_type (gdbarch, regnum);
+}
+
 /* Return the pseudo register name corresponding to register regnum.  */
 
 static const char *
@@ -2851,6 +2867,10 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   const struct tdesc_feature *feature;
   int num_regs = 0;
   int num_pseudo_regs = 0;
+  bool ilp32 = FALSE;
+
+  if (info.bfd_arch_info->mach == bfd_mach_aarch64_ilp32)
+    ilp32 = TRUE;
 
   /* Ensure we always have a target descriptor.  */
   if (!tdesc_has_registers (tdesc))
@@ -2908,6 +2928,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
        best_arch != NULL;
        best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
     {
+      /* ILP32 and LP64 are incompatible. */
+      if (gdbarch_tdep (arches->gdbarch)->ilp32 != ilp32)
+	continue;
       /* Found a match.  */
       break;
     }
@@ -2926,6 +2949,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   tdep->lowest_pc = 0x20;
   tdep->jb_pc = -1;		/* Longjump support not enabled by default.  */
   tdep->jb_elt_size = 8;
+  tdep->ilp32 = ilp32;
 
   set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
   set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
@@ -2968,9 +2992,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   set_gdbarch_float_bit (gdbarch, 32);
   set_gdbarch_double_bit (gdbarch, 64);
   set_gdbarch_long_double_bit (gdbarch, 128);
-  set_gdbarch_long_bit (gdbarch, 64);
+  set_gdbarch_long_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_long_long_bit (gdbarch, 64);
-  set_gdbarch_ptr_bit (gdbarch, 64);
+  set_gdbarch_ptr_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_char_signed (gdbarch, 0);
   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
@@ -3012,6 +3036,13 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 
   tdesc_use_registers (gdbarch, tdesc, tdesc_data);
 
+  if (ilp32)
+    {
+      /* Override tdesc_register_type to adjust the types of $PC and
+	 $SP in ILP32.  */
+      set_gdbarch_register_type (gdbarch, aarch64_ilp32_register_type);
+    }
+
   /* Add standard register aliases.  */
   for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
     user_reg_add (gdbarch, aarch64_register_aliases[i].name,
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 85c6a97..87d36b6 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -97,6 +97,9 @@ struct gdbarch_tdep
 
   /* syscall record.  */
   int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
+  /* If this is ILP32 or LP64.  */
+  bool ilp32;
+
 };
 
 extern struct target_desc *tdesc_aarch64;
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index 334310b..e31d5c5 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -484,7 +484,12 @@ aarch64_linux_read_description (void)
 
   is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
 
-  if (is_elf64)
+  /* There are problems with ptrace when gdbserver is 32 bits and the
+     program being debugged is 64 bits.  */
+  if (sizeof (void *) == 4 && is_elf64)
+    error (_("Can't debug 64-bit process with 32-bit GDBserver"));
+
+  if (machine == EM_AARCH64)
     return tdesc_aarch64;
   else
     return tdesc_arm_with_neon;

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On 17-01-27 14:25:39, Steve Ellcey wrote:
> That patch seems reasonable and it fixed some test failures I had
> in the glibc testsuite but it is breaking gdb.????If I undo this
> patch by making this change to bfd/cpu-aarch64.c:
> 
> ??static const bfd_arch_info_type bfd_aarch64_arch_ilp32 =
> -????N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, NULL);
> +????N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 64, FALSE, NULL);
>

This changes the word size and address size, which is used to determine
the inferior is arm or aarch64 by checking "bits_per_word == 32" in
multi-arch debugging.  You can find some instances of such check in
aarch64-linux-nat.c.  If the bits_per_word is 32 in ILP32, GDB thinks
the inferior is an ARM one, rather than an AArch64 ILP32 one. which is
wrong.  We need to tweak the condition above to correctly identify the
ARM inferior.

> Then gdb starts working again and I can debug 32 bit programs.
> 
> I am not sure how this change to the ILP32 aarch64 bfd description
> is affecting gdb and why this change would break things.????Do you
> know why this change messes up gdb?
> 

D0 you compare the ILP32 gdb test result with normal aarch64 one?

> +
>  /* Return the pseudo register name corresponding to register regnum.  */
>  
>  static const char *
> @@ -2851,6 +2867,10 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
>    const struct tdesc_feature *feature;
>    int num_regs = 0;
>    int num_pseudo_regs = 0;
> +  bool ilp32 = FALSE;
> +

s/FALSE/false/

> +  if (info.bfd_arch_info->mach == bfd_mach_aarch64_ilp32)
> +    ilp32 = TRUE;

s/TRUE/true/

-- 
Yao 

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

[-- Attachment #1: Type: text/plain, Size: 3665 bytes --]

On Sun, 2017-01-29 at 22:40 +0000, Yao Qi wrote:

> This changes the word size and address size, which is used to determine
> the inferior is arm or aarch64 by checking "bits_per_word == 32" in
> multi-arch debugging.  You can find some instances of such check in
> aarch64-linux-nat.c.  If the bits_per_word is 32 in ILP32, GDB thinks
> the inferior is an ARM one, rather than an AArch64 ILP32 one. which is
> wrong.  We need to tweak the condition above to correctly identify the
> ARM inferior.
> 
> Do you compare the ILP32 gdb test result with normal aarch64 one?

OK, I fixed up arch64-linux-nat.c and didn't find any other places were
the bits_per_word was being checked and I fixed the TRUE/true
FALSE/false constants.  If I run gdb without any changes or with this
patch but debugging 64 bit code I get around 500 failures.  The number
doesn't seem to be constant, I have gotten anywhere from 488 to 503
failures testing the same code.  My last run had:

# of expected passes            30428
# of unexpected failures        503
# of expected failures          53
# of unknown successes          2
# of known failures             64
# of untested testcases         66
# of unresolved testcases       6
# of unsupported tests          293

Many of the failures seem to be thread related and I see a lot of
messages about timeouts and 'program is no longer running'.  When
I run gdb on 32 bit programs with:

	RUNTESTFLAGS="--target_board=unix/-mabi=ilp32"

I get 700+ failures.  My last run had:

# of expected passes            29482
# of unexpected failures        740
# of expected failures          30
# of unknown successes          2
# of known failures             65
# of untested testcases         79
# of unresolved testcases       4
# of unsupported tests          288

So there are more failures in ILP32 mode but there seem to be enough
passes that I think it still makes sense to check in the patch to get
some gdb functionality working.

Here is the latest patch.

Steve Ellcey
sellcey@cavium.com


gdb ChangeLog:

2017-01-31  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>
	    Yao Qi  <yao.qi@linaro.org>

	* aarch64-linux-nat.c (IS_ARM32): New macro.
	(fetch_gregs_from_thread): Use IS_ARM32 macro.
	(store_gregs_to_thread): Ditto.
	(fetch_fpregs_from_thread): Ditto.
	(store_fpregs_to_thread): Ditto.
	(ps_get_thread_area): Ditto.
	(aarch64_linux_siginfo_fixup): Ditto.
	* aarch64-linux-tdep.c (aarch64_linux_init_abi): Set link
	map offsets to 32 or 64 bits.
	* aarch64-tdep.c (aarch64_ilp32_register_type): New function.
	(aarch64_gdbarch_init): Setup ILP32 support.
	Make sure the gdbarches have compatible ilp32 flags.
	Set long and ptr sizes correctly for ilp32.
	* aarch64-tdep.h (gdbarch_tdep) <ilp32>: New field.

gdbserver ChangeLog:

2017-01-31  Andrew Pinski  <apinski@cavium.com>
	    Steve Ellcey  <sellcey@cavium.com>

	* linux-aarch64-low.c (aarch64_linux_read_description): Use
	machine instead of is_elf64 to determine architecture.  Give an
	error when using 32 bit gdbserver on 64 bit program.

[-- Attachment #2: gdb.patch --]
[-- Type: text/x-patch, Size: 8110 bytes --]

diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index 0d472e2..f6fd19a 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -49,6 +49,9 @@
 #define TRAP_HWBKPT 0x0004
 #endif
 
+/* Check if we are on arm (as opposed to aarch64).  */
+#define IS_ARM32(arch) (gdbarch_bfd_arch_info(arch)->mach == bfd_mach_arm)
+
 /* Per-process data.  We don't bind this to a per-inferior registry
    because of targets like x86 GNU/Linux that need to keep track of
    processes that aren't bound to any inferior (e.g., fork children,
@@ -166,7 +169,7 @@ fetch_gregs_from_thread (struct regcache *regcache)
   tid = ptid_get_lwp (inferior_ptid);
 
   iovec.iov_base = &regs;
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     iovec.iov_len = 18 * 4;
   else
     iovec.iov_len = sizeof (regs);
@@ -175,7 +178,7 @@ fetch_gregs_from_thread (struct regcache *regcache)
   if (ret < 0)
     perror_with_name (_("Unable to fetch general registers."));
 
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
   else
     {
@@ -203,7 +206,7 @@ store_gregs_to_thread (const struct regcache *regcache)
   tid = ptid_get_lwp (inferior_ptid);
 
   iovec.iov_base = &regs;
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     iovec.iov_len = 18 * 4;
   else
     iovec.iov_len = sizeof (regs);
@@ -212,7 +215,7 @@ store_gregs_to_thread (const struct regcache *regcache)
   if (ret < 0)
     perror_with_name (_("Unable to fetch general registers."));
 
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
   else
     {
@@ -248,7 +251,7 @@ fetch_fpregs_from_thread (struct regcache *regcache)
 
   iovec.iov_base = &regs;
 
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     {
       iovec.iov_len = VFP_REGS_SIZE;
 
@@ -295,7 +298,7 @@ store_fpregs_to_thread (const struct regcache *regcache)
 
   iovec.iov_base = &regs;
 
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     {
       iovec.iov_len = VFP_REGS_SIZE;
 
@@ -328,7 +331,7 @@ store_fpregs_to_thread (const struct regcache *regcache)
 			      (char *) &regs.fpcr);
     }
 
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     {
       ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
       if (ret < 0)
@@ -460,8 +463,7 @@ ps_err_e
 ps_get_thread_area (struct ps_prochandle *ph,
 		    lwpid_t lwpid, int idx, void **base)
 {
-  int is_64bit_p
-    = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64);
+  int is_64bit_p = !IS_ARM32 (target_gdbarch ());
 
   return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
 }
@@ -517,7 +519,7 @@ aarch64_linux_siginfo_fixup (siginfo_t *native, gdb_byte *inf, int direction)
 
   /* Is the inferior 32-bit?  If so, then do fixup the siginfo
      object.  */
-  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
+  if (IS_ARM32 (gdbarch))
     {
       if (direction == 0)
 	aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c
index b94ccb2..6d0c3bd 100644
--- a/gdb/aarch64-linux-tdep.c
+++ b/gdb/aarch64-linux-tdep.c
@@ -1000,8 +1000,12 @@ aarch64_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
 
   linux_init_abi (info, gdbarch);
 
-  set_solib_svr4_fetch_link_map_offsets (gdbarch,
-					 svr4_lp64_fetch_link_map_offsets);
+  if (tdep->ilp32)
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_ilp32_fetch_link_map_offsets);
+  else
+    set_solib_svr4_fetch_link_map_offsets (gdbarch,
+					   svr4_lp64_fetch_link_map_offsets);
 
   /* Enable TLS support.  */
   set_gdbarch_fetch_tls_load_module_address (gdbarch,
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 801c03d..67f1a2e 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2091,6 +2091,22 @@ aarch64_gen_return_address (struct gdbarch *gdbarch,
 }
 \f
 
+/* Implement the "register_type" gdbarch method.
+   Adjust the register type of $PC and $SP on ILP32.  */
+
+static struct type *
+aarch64_ilp32_register_type (struct gdbarch *gdbarch, int regnum)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+  gdb_assert (tdep->ilp32);
+
+  if (regnum == AARCH64_SP_REGNUM || regnum == AARCH64_PC_REGNUM)
+    return builtin_type (gdbarch)->builtin_uint64;
+  else
+    return tdesc_register_type (gdbarch, regnum);
+}
+
 /* Return the pseudo register name corresponding to register regnum.  */
 
 static const char *
@@ -2851,6 +2867,10 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   const struct tdesc_feature *feature;
   int num_regs = 0;
   int num_pseudo_regs = 0;
+  bool ilp32 = false;
+
+  if (info.bfd_arch_info->mach == bfd_mach_aarch64_ilp32)
+    ilp32 = true;
 
   /* Ensure we always have a target descriptor.  */
   if (!tdesc_has_registers (tdesc))
@@ -2908,6 +2928,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
        best_arch != NULL;
        best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info))
     {
+      /* ILP32 and LP64 are incompatible. */
+      if (gdbarch_tdep (arches->gdbarch)->ilp32 != ilp32)
+	continue;
       /* Found a match.  */
       break;
     }
@@ -2926,6 +2949,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   tdep->lowest_pc = 0x20;
   tdep->jb_pc = -1;		/* Longjump support not enabled by default.  */
   tdep->jb_elt_size = 8;
+  tdep->ilp32 = ilp32;
 
   set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call);
   set_gdbarch_frame_align (gdbarch, aarch64_frame_align);
@@ -2968,9 +2992,9 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
   set_gdbarch_float_bit (gdbarch, 32);
   set_gdbarch_double_bit (gdbarch, 64);
   set_gdbarch_long_double_bit (gdbarch, 128);
-  set_gdbarch_long_bit (gdbarch, 64);
+  set_gdbarch_long_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_long_long_bit (gdbarch, 64);
-  set_gdbarch_ptr_bit (gdbarch, 64);
+  set_gdbarch_ptr_bit (gdbarch, ilp32 ? 32 : 64);
   set_gdbarch_char_signed (gdbarch, 0);
   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
@@ -3012,6 +3036,13 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 
   tdesc_use_registers (gdbarch, tdesc, tdesc_data);
 
+  if (ilp32)
+    {
+      /* Override tdesc_register_type to adjust the types of $PC and
+	 $SP in ILP32.  */
+      set_gdbarch_register_type (gdbarch, aarch64_ilp32_register_type);
+    }
+
   /* Add standard register aliases.  */
   for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++)
     user_reg_add (gdbarch, aarch64_register_aliases[i].name,
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index 85c6a97..87d36b6 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -97,6 +97,9 @@ struct gdbarch_tdep
 
   /* syscall record.  */
   int (*aarch64_syscall_record) (struct regcache *regcache, unsigned long svc_number);
+  /* If this is ILP32 or LP64.  */
+  bool ilp32;
+
 };
 
 extern struct target_desc *tdesc_aarch64;
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index 334310b..e31d5c5 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -484,7 +484,12 @@ aarch64_linux_read_description (void)
 
   is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
 
-  if (is_elf64)
+  /* There are problems with ptrace when gdbserver is 32 bits and the
+     program being debugged is 64 bits.  */
+  if (sizeof (void *) == 4 && is_elf64)
+    error (_("Can't debug 64-bit process with 32-bit GDBserver"));
+
+  if (machine == EM_AARCH64)
     return tdesc_aarch64;
   else
     return tdesc_arm_with_neon;

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On 17-01-31 15:15:59, Steve Ellcey wrote:
> On Sun, 2017-01-29 at 22:40 +0000, Yao Qi wrote:
>
> > This changes the word size and address size, which is used to determine
> > the inferior is arm or aarch64 by checking "bits_per_word == 32" in
> > multi-arch debugging.????You can find some instances of such check in
> > aarch64-linux-nat.c.????If the bits_per_word is 32 in ILP32, GDB thinks
> > the inferior is an ARM one, rather than an AArch64 ILP32 one. which is
> > wrong.????We need to tweak the condition above to correctly identify the
> > ARM inferior.
> >??
> > Do you compare the ILP32 gdb test result with normal aarch64 one?
>
> OK, I fixed up??arch64-linux-nat.c and didn't find any other places were
> the bits_per_word was being checked and I fixed the TRUE/true
> FALSE/false constants. ??If I run gdb without any changes or with this
> patch but debugging 64 bit code I get around 500 failures. ??The number
> doesn't seem to be constant, I have gotten anywhere from 488 to 503
> failures testing the same code. ??My last run had:
>
> # of expected passes????????????????????????30428
> # of unexpected failures????????????????503
> # of expected failures????????????????????53
> # of unknown successes????????????????????2
> # of known failures??????????????????????????64
> # of untested testcases??????????????????66
> # of unresolved testcases??????????????6
> # of unsupported tests????????????????????293
>
> Many of the failures seem to be thread related and I see a lot of
> messages about timeouts and 'program is no longer running'. ??When

If you get 500 fails in vanilla GDB on aarch64-linux, there must be
something wrong.  We only have 36 fails in buildbot slave.

What is your compiler, library and kernel?  They may have some local
ilp32 patches.

> I run gdb on 32 bit programs with:
>
> RUNTESTFLAGS="--target_board=unix/-mabi=ilp32"
>
> I get 700+ failures. ??My last run had:
>
> # of expected passes????????????????????????29482
> # of unexpected failures????????????????740
> # of expected failures????????????????????30
> # of unknown successes????????????????????2
> # of known failures??????????????????????????65
> # of untested testcases??????????????????79
> # of unresolved testcases??????????????4
> # of unsupported tests????????????????????288
>
> So there are more failures in ILP32 mode but there seem to be enough
> passes that I think it still makes sense to check in the patch to get
> some gdb functionality working.
>

"even if GDB is horribly broken, many tests will still pass."
https://sourceware.org/gdb/wiki/TestingGDB#Caveat_emptor

500 fails and 240 regressions are not a good signal.
I don't see anything wrong from ilp32 gdb patch here, but I suspect
these 500 fails are caused by some bugs or oversights in other parts,
such as kernel or gliblc.  aarch64-linux GDB test shouldn't have 500 fails on
aarch64-linux system with ilp32 enabled.  Could you dig it out?

-- 
Yao

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On Wed, Feb 1, 2017 at 10:20 PM, Yao Qi <qiyaoltc@gmail.com> wrote:
> something wrong.  We only have 36 fails in buildbot slave.
>

https://gdb-build.sergiodj.net/builders/Ubuntu-AArch64-m64/builds/1337/steps/regressions/logs/stdio

-- 
Yao (齐尧)

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

On Wed, 2017-02-01 at 22:20 +0000, Yao Qi wrote:
> 
> If you get 500 fails in vanilla GDB on aarch64-linux, there must be
> something wrong.  We only have 36 fails in buildbot slave.
> 
> What is your compiler, library and kernel?  They may have some local
> ilp32 patches.

My compiler, library, and kernel do have ILP32 patches, though I am
building gdb in LP64 mode.  Those patches haven't caused new failures
in the GCC testsuite and only a couple of regressions in the glibc
testsuite.

I have heard there are some kernel bugs, fixed in 4.10, that could be
causing some of these failures.  I am using a 4.9 kernel with ILP32
patches.  I was running the testsuite in parallel mode and I have also
heard that could cause problems, I just redid it in serial mode to see
if that helps.  I still got 460 failures when compiling the tests in
LP64 mode.

347 of them are in gdb.threads, with 207 being messages like:

FAIL: gdb.threads/clone-attach-detach.exp: fg attach 2: detach (the program is no longer running)

I.e. a message containing '(the program is no longer running)'  I also
noticed that most of the tests that are failing have the name 'attach'
in them.  There are 97 tests in gdb.base failing and about 2/3 of them
also have some reference to 'attach'. So I think I have some issue
withgdb attaching to a process.  For example, the first failures are:

FAIL: gdb.base/attach-pie-noexec.exp: info shared
FAIL: gdb.base/attach-twice.exp: attach
FAIL: gdb.base/attach.exp: attach1, after setting file
FAIL: gdb.base/attach.exp: attach1 detach (the program is no longer
running)
FAIL: gdb.base/attach.exp: attach2, with no file
FAIL: gdb.base/attach.exp: after attach2, set should_exit
FAIL: gdb.base/attach.exp: continue to breakpoint: postloop (the
program is no longer running)
FAIL: gdb.base/attach.exp: continue until exit at after attach2, exit
(the program is no longer running)
FAIL: gdb.base/attach.exp: attach when process' a.out not in cwd
FAIL: gdb.base/attach.exp: continue until exit (the program is no
longer running)
FAIL: gdb.base/attach.exp: starting with --pid
FAIL: gdb.base/attach.exp: cmdline attach run: run to prompt


Steve Ellcey
sellcey@cavium.com

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

It looks like I am having a problem with ptrace.  From gdb.log:

Attaching to program: /home/ubuntu/sellcey/gdb-std/obj/binutils/gdb/testsuite/outputs/gdb.base/attach/attach, process 7631
ptrace: Operation not permitted.
(gdb) FAIL: gdb.base/attach.exp: attach1, after setting file
print should_exit
$1 = 0


Steve Ellcey
sellcey@cavium.com

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On 17-02-01 16:39:56, Steve Ellcey wrote:
> It looks like I am having a problem with ptrace.  From gdb.log:
> 
> Attaching to program: /home/ubuntu/sellcey/gdb-std/obj/binutils/gdb/testsuite/outputs/gdb.base/attach/attach, process 7631
> ptrace: Operation not permitted.

Hi Steve,
This is a common ptrace attach permission issue.  You can
"echo 0 > /proc/sys/kernel/yama/ptrace_scope" or modify it in some config
file /etc/sysctl.d/10-ptrace.conf (different distro may have different
path).

-- 
Yao (齐尧)

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Steve Ellcey]

On Thu, 2017-02-02 at 09:51 +0000, Yao Qi wrote:
> On 17-02-01 16:39:56, Steve Ellcey wrote:
> > 
> > It looks like I am having a problem with ptrace.  From gdb.log:
> > 
> > Attaching to program: /home/ubuntu/sellcey/gdb-
> > std/obj/binutils/gdb/testsuite/outputs/gdb.base/attach/attach,
> > process 7631
> > ptrace: Operation not permitted.
> Hi Steve,
> This is a common ptrace attach permission issue.  You can
> "echo 0 > /proc/sys/kernel/yama/ptrace_scope" or modify it in some config
> file /etc/sysctl.d/10-ptrace.conf (different distro may have different
> path).


OK, the pthread permission problem was the main cause of my LP64
failures.  I fixed that, ran the standard gdb testsuite on unpatched
code in parallel mode and got 99 failures.  If I run in sequential mode
I got 74 failures.  Updating the kernel got me to 72 failures.  Many of
these are timeouts so I may need to increase that.  If I ignore the
timeouts I have 39 failures, which is pretty close to the 36 from the
buildbot testing though the list of what is and is not failing is
different.

I then ran the testing with 64 bit programs using the patched sources
and got about the same results as the unpatched sources on my
machine.  There was one failure that went away (a timeout):

FAIL: gdb.threads/step-over-trips-on-watchpoint.exp: displaced=off: no thread-specific bp: continue: continue (timeout)

And two that appeared:

FAIL: gdb.base/watchpoint.exp: next over buffer set
FAIL: gdb.base/watchpoint.exp: next over ptr init

When I tested gdb on ILP32 executables I got 235 failures, only 3 of
which were timeouts.  So there are definitely some issues there.  One
thing I noticed is references to ldd.  The ldd I have in my path does
not understand ILP32 executables so that is probably causing some
failures.  I will fix that and see what else I can find to explain the
ILP32 failures.

Steve Ellcey
sellcey@cavium.com

Re: [PATCH] Patch 2 of 2 for aarch64 ILP32 support in gdb

[Yao Qi]

On 17-02-02 14:03:41, Steve Ellcey wrote:
> OK, the pthread permission problem was the main cause of my LP64
> failures.  I fixed that, ran the standard gdb testsuite on unpatched
> code in parallel mode and got 99 failures.  If I run in sequential mode
> I got 74 failures.  Updating the kernel got me to 72 failures.  Many of
> these are timeouts so I may need to increase that.  If I ignore the
> timeouts I have 39 failures, which is pretty close to the 36 from the
> buildbot testing though the list of what is and is not failing is
> different.

The result looks reasonable now.

> 
> I then ran the testing with 64 bit programs using the patched sources
> and got about the same results as the unpatched sources on my
> machine.  There was one failure that went away (a timeout):
> 
> FAIL: gdb.threads/step-over-trips-on-watchpoint.exp: displaced=off: no thread-specific bp: continue: continue (timeout)
> 
> And two that appeared:
> 
> FAIL: gdb.base/watchpoint.exp: next over buffer set
> FAIL: gdb.base/watchpoint.exp: next over ptr init
> 
> When I tested gdb on ILP32 executables I got 235 failures, only 3 of
> which were timeouts.  So there are definitely some issues there.  One
> thing I noticed is references to ldd.  The ldd I have in my path does
> not understand ILP32 executables so that is probably causing some
> failures.  I will fix that and see what else I can find to explain the
> ILP32 failures.
> 

OK, great!

-- 
Yao (齐尧)