From: Bhushan Attarde <bhushan.attarde@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <Maciej.Rozycki@imgtec.com>, <Matthew.Fortune@imgtec.com>,
<James.Hogan@imgtec.com>, <Andrew.Bennett@imgtec.com>,
<Jaydeep.Patil@imgtec.com>,
Bhushan Attarde <bhushan.attarde@imgtec.com>
Subject: [PATCH 06/24] mips-linux-nat: pick fp64 target description when appropriate
Date: Mon, 27 Jun 2016 14:50:00 -0000 [thread overview]
Message-ID: <1467038991-6600-6-git-send-email-bhushan.attarde@imgtec.com> (raw)
In-Reply-To: <1467038991-6600-1-git-send-email-bhushan.attarde@imgtec.com>
This is decided by reading MIPS FIR register using prace and checking it's
F64 bit.
gdb/ChangeLog:
* mips-linux-nat.c: Include "features/mips-fpu64-linux.c" and
"features/mips-fpu64-dsp-linux.c".
(FIR_F64): New definaition for F64 bit of FIR register.
(supply_fpregset, fill_fpregset): Use 64-bit functions.
(mips_linux_read_description): New have_fpu64 variable to indicate 64-bit
FPU target.
(initialize_tdesc_mips_fpu64_linux, initialize_tdesc_mips_fpu64_dsp_linux):
Add initializer functions for fpu64 and fpu64_dsp targets.
---
gdb/mips-linux-nat.c | 55 +++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 44 insertions(+), 11 deletions(-)
diff --git a/gdb/mips-linux-nat.c b/gdb/mips-linux-nat.c
index 627c652..543cc36 100644
--- a/gdb/mips-linux-nat.c
+++ b/gdb/mips-linux-nat.c
@@ -40,6 +40,8 @@
#include "features/mips-linux.c"
#include "features/mips-dsp-linux.c"
+#include "features/mips-fpu64-linux.c"
+#include "features/mips-fpu64-dsp-linux.c"
#include "features/mips64-linux.c"
#include "features/mips64-dsp-linux.c"
@@ -55,6 +57,8 @@
#define PTRACE_SETREGSET 0x4205
#endif
+#define FIR_F64 (1 << 22)
+
/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
we'll clear this and use PTRACE_PEEKUSER instead. */
static int have_ptrace_regsets = 1;
@@ -203,22 +207,16 @@ fill_gregset (const struct regcache *regcache,
void
supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
{
- if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
- mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp);
- else
- mips64_supply_fpregset (regcache,
- (const mips64_elf_fpregset_t *) fpregsetp);
+ mips64_supply_fpregset (regcache,
+ (const mips64_elf_fpregset_t *) fpregsetp);
}
void
fill_fpregset (const struct regcache *regcache,
gdb_fpregset_t *fpregsetp, int regno)
{
- if (mips_isa_regsize (get_regcache_arch (regcache)) == 4)
- mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno);
- else
- mips64_fill_fpregset (regcache,
- (mips64_elf_fpregset_t *) fpregsetp, regno);
+ mips64_fill_fpregset (regcache,
+ (mips64_elf_fpregset_t *) fpregsetp, regno);
}
@@ -604,8 +602,41 @@ mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p)
static const struct target_desc *
mips_linux_read_description (struct target_ops *ops)
{
+ const struct target_desc *tdescs[2][2] =
+ {
+ /* have_fpu64 = 0 have_fpu64 = 1 */
+ { tdesc_mips_linux, tdesc_mips_fpu64_linux }, /* have_dsp = 0 */
+ { tdesc_mips_dsp_linux, tdesc_mips_fpu64_dsp_linux }, /* have_dsp = 1 */
+ };
+
static int have_dsp = -1;
+ static int have_fpu64 = -1;
+ if (have_fpu64 < 0)
+ {
+ int tid;
+ long fir;
+
+ tid = ptid_get_lwp (inferior_ptid);
+ if (tid == 0)
+ tid = ptid_get_pid (inferior_ptid);
+
+ /* Try peeking at FIR.F64 bit */
+ errno = 0;
+ fir = ptrace (PTRACE_PEEKUSER, tid, FPC_EIR, 0);
+ switch (errno)
+ {
+ case 0:
+ have_fpu64 = !!(fir & FIR_F64);
+ break;
+ case EIO:
+ have_fpu64 = 0;
+ break;
+ default:
+ perror_with_name ("ptrace");
+ break;
+ }
+ }
if (have_dsp < 0)
{
int tid;
@@ -633,7 +664,7 @@ mips_linux_read_description (struct target_ops *ops)
/* Report that target registers are a size we know for sure
that we can get from ptrace. */
if (_MIPS_SIM == _ABIO32)
- return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
+ return tdescs[have_dsp][have_fpu64];
else
return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
}
@@ -990,6 +1021,8 @@ triggers a breakpoint or watchpoint."),
/* Initialize the standard target descriptions. */
initialize_tdesc_mips_linux ();
initialize_tdesc_mips_dsp_linux ();
+ initialize_tdesc_mips_fpu64_linux ();
+ initialize_tdesc_mips_fpu64_dsp_linux ();
initialize_tdesc_mips64_linux ();
initialize_tdesc_mips64_dsp_linux ();
}
--
1.9-rc2
next prev parent reply other threads:[~2016-06-27 14:50 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-27 14:50 [PATCH 01/24] MIPS: Handle run-time reconfigurable FPR size Bhushan Attarde
2016-06-27 14:50 ` [PATCH 08/24] MIPS: Convert FP mode to enum and put fp registers into fp reggroup Bhushan Attarde
2016-06-27 14:50 ` [PATCH 10/24] MIPS: override fscr/fir types and print control registers specially Bhushan Attarde
2016-06-27 14:50 ` [PATCH 03/24] regcache: handle invalidated regcache Bhushan Attarde
2016-10-21 22:42 ` Maciej W. Rozycki
2016-06-27 14:50 ` Bhushan Attarde [this message]
2016-06-27 14:50 ` [PATCH 11/24] MIPS: Add support for hybrid fp32/fp64 mode Bhushan Attarde
2016-06-27 14:51 ` [PATCH 07/24] MIPS: Make Linux restart register more dynamic Bhushan Attarde
2016-06-27 14:51 ` [PATCH 13/24] Add MIPS MSA GDB target descriptions Bhushan Attarde
2016-06-27 14:51 ` [PATCH 18/24] mips-linux-nat: get msa registers Bhushan Attarde
2016-06-27 14:51 ` [PATCH 02/24] Add MIPS32 FPU64 GDB target descriptions Bhushan Attarde
2016-10-12 12:42 ` Maciej W. Rozycki
2016-10-12 13:58 ` James Hogan
2016-10-12 16:30 ` Maciej W. Rozycki
2016-10-12 18:05 ` James Hogan
2016-10-12 22:04 ` Maciej W. Rozycki
2016-10-13 10:09 ` Matthew Fortune
2016-10-21 19:17 ` Maciej W. Rozycki
2016-10-21 19:24 ` Maciej W. Rozycki
2016-06-27 14:51 ` [PATCH 04/24] Add MIPS Config5 register related support Bhushan Attarde
2016-06-27 14:51 ` [PATCH 23/24] MIPS R6 opcode table shuffle for LDC2/SDC2 Bhushan Attarde
2016-06-27 14:51 ` [PATCH 21/24] MIPSR6 support for GDB Bhushan Attarde
2016-07-29 21:10 ` Maciej W. Rozycki
2016-06-27 14:51 ` [PATCH 05/24] MIPS: Add config5 to MIPS GDB target descriptions Bhushan Attarde
2016-06-27 14:51 ` [PATCH 24/24] MIPS R6 forbidden slot support Bhushan Attarde
2016-06-27 14:51 ` [PATCH 12/24] o32 sigframe unwinding with FR1 Bhushan Attarde
2016-06-27 14:51 ` [PATCH 14/24] Implement core MSA stuff Bhushan Attarde
2016-06-27 14:51 ` [PATCH 20/24] Drop FP and MSA control registers from default info registers Bhushan Attarde
2016-06-27 14:51 ` [PATCH 22/24] Support all new ABIs when detecting if an FPU is present Bhushan Attarde
2016-06-27 14:51 ` [PATCH 19/24] Add MIPS MSA vector branch instruction support Bhushan Attarde
2016-06-27 14:51 ` [PATCH 09/24] MIPS: Enhance cooked FP format Bhushan Attarde
2016-07-25 14:03 ` [PATCH 01/24] MIPS: Handle run-time reconfigurable FPR size Maciej W. Rozycki
2016-10-18 17:37 ` Maciej W. Rozycki
2016-11-08 19:46 ` Yao Qi
2016-11-10 12:43 ` Maciej W. Rozycki
2016-11-11 12:29 ` Yao Qi
2016-12-02 2:31 ` Maciej W. Rozycki
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