[ltt-dev] [URCU PATCH v2 1/2] caa: let per-arch files provide cmm_smp_* barriers

[ltt-dev] [URCU PATCH v2 1/2] caa: let per-arch files provide cmm_smp_* barriers

[Paolo Bonzini]

x86 instructions lfence and sfence are rarely needed, and we want
the cmm_smp_rmb/cmm_smp_wmb macros to be simple compiler barriers.
So, let the per-arch files override the default definitions in
arch/generic.h.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch/generic.h |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/urcu/arch/generic.h b/urcu/arch/generic.h
index 100d3c6..1ea7f59 100644
--- a/urcu/arch/generic.h
+++ b/urcu/arch/generic.h
@@ -100,22 +100,50 @@ extern "C" {
 #endif
 
 #ifdef CONFIG_RCU_SMP
+#ifndef cmm_smp_mb
 #define cmm_smp_mb()	cmm_mb()
+#endif
+#ifndef cmm_smp_rmb
 #define cmm_smp_rmb()	cmm_rmb()
+#endif
+#ifndef cmm_smp_wmb
 #define cmm_smp_wmb()	cmm_wmb()
+#endif
+#ifndef cmm_smp_mc
 #define cmm_smp_mc()	cmm_mc()
+#endif
+#ifndef cmm_smp_rmc
 #define cmm_smp_rmc()	cmm_rmc()
+#endif
+#ifndef cmm_smp_wmc
 #define cmm_smp_wmc()	cmm_wmc()
+#endif
+#ifndef cmm_smp_read_barrier_depends
 #define cmm_smp_read_barrier_depends()	cmm_read_barrier_depends()
+#endif
 #else
+#ifndef cmm_smp_mb
 #define cmm_smp_mb()	cmm_barrier()
+#endif
+#ifndef cmm_smp_rmb
 #define cmm_smp_rmb()	cmm_barrier()
+#endif
+#ifndef cmm_smp_wmb
 #define cmm_smp_wmb()	cmm_barrier()
+#endif
+#ifndef cmm_smp_mc
 #define cmm_smp_mc()	cmm_barrier()
+#endif
+#ifndef cmm_smp_rmc
 #define cmm_smp_rmc()	cmm_barrier()
+#endif
+#ifndef cmm_smp_wmc
 #define cmm_smp_wmc()	cmm_barrier()
+#endif
+#ifndef cmm_smp_read_barrier_depends
 #define cmm_smp_read_barrier_depends()
 #endif
+#endif
 
 #ifndef caa_cpu_relax
 #define caa_cpu_relax()		cmm_barrier()
-- 
1.7.6

[ltt-dev] [URCU PATCH v2 2/2] caa: do not generate code for smp_rmb/smp_wmb on x86_64, smp_rmb on i686

[Paolo Bonzini]

Usually we can assume no accesses to write-combining memory occur,
and also that there are no non-temporal load/stores (people would presumably
write those with assembly or intrinsics and put appropriate lfence/sfence
manually).  In this case rmb and wmb are no-ops on x86.  Define cmm_smp_rmb
and cmm_smp_wmb to be the "common" operations, while leaving cmm_rmb
and cmm_wmb in place for more sophisticated uses.

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch/x86.h |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
index 9e5411f..c399c25 100644
--- a/urcu/arch/x86.h
+++ b/urcu/arch/x86.h
@@ -33,18 +33,35 @@ extern "C" {
 
 #ifdef CONFIG_RCU_HAVE_FENCE
 #define cmm_mb()    asm volatile("mfence":::"memory")
+
+/*
+ * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when
+ * using SSE or working with I/O areas.  cmm_smp_rmb/cmm_smp_wmb are
+ * only compiler barriers, which is enough for general use.
+ */
 #define cmm_rmb()   asm volatile("lfence":::"memory")
 #define cmm_wmb()   asm volatile("sfence"::: "memory")
-#else
+
 /*
- * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
- * nop for these.
+ * IDT WinChip supports weak store ordering, and the kernel may enable it
+ * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
+ * However, this doesn't happen on any processor that has *fence instructions.
  */
+#define cmm_smp_wmb() cmm_barrier()
+#else
 #define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
 #define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
 #define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
 #endif
 
+/*
+ * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor
+ * systems, due to an erratum, but the Linux kernel says that "Even distro
+ * kernels should think twice before enabling this".  Hence never generate
+ * code for it, even on machines that have no *fence instructions.
+ */
+#define cmm_smp_rmb() cmm_barrier()
+
 #define caa_cpu_relax()	asm volatile("rep; nop" : : : "memory");
 
 #define rdtscll(val)							  \
-- 
1.7.6

[ltt-dev] [URCU PATCH v2 2/2] caa: do not generate code for smp_rmb/smp_wmb on x86_64, smp_rmb on i686

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> Usually we can assume no accesses to write-combining memory occur,
> and also that there are no non-temporal load/stores (people would presumably
> write those with assembly or intrinsics and put appropriate lfence/sfence
> manually).  In this case rmb and wmb are no-ops on x86.  Define cmm_smp_rmb
> and cmm_smp_wmb to be the "common" operations, while leaving cmm_rmb
> and cmm_wmb in place for more sophisticated uses.
> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch/x86.h |   23 ++++++++++++++++++++---
>  1 files changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/urcu/arch/x86.h b/urcu/arch/x86.h
> index 9e5411f..c399c25 100644
> --- a/urcu/arch/x86.h
> +++ b/urcu/arch/x86.h
> @@ -33,18 +33,35 @@ extern "C" {
>  
>  #ifdef CONFIG_RCU_HAVE_FENCE
>  #define cmm_mb()    asm volatile("mfence":::"memory")
> +
> +/*
> + * Define cmm_rmb/cmm_wmb to "strict" barriers that may be needed when
> + * using SSE or working with I/O areas.  cmm_smp_rmb/cmm_smp_wmb are
> + * only compiler barriers, which is enough for general use.
> + */
>  #define cmm_rmb()   asm volatile("lfence":::"memory")
>  #define cmm_wmb()   asm volatile("sfence"::: "memory")
> -#else
> +
>  /*
> - * Some non-Intel clones support out of order store. cmm_wmb() ceases to be a
> - * nop for these.
> + * IDT WinChip supports weak store ordering, and the kernel may enable it
> + * under our feet; cmm_smp_wmb() ceases to be a nop for these processors.
> + * However, this doesn't happen on any processor that has *fence instructions.
>   */
> +#define cmm_smp_wmb() cmm_barrier()
> +#else
>  #define cmm_mb()    asm volatile("lock; addl $0,0(%%esp)":::"memory")
>  #define cmm_rmb()   asm volatile("lock; addl $0,0(%%esp)":::"memory")
>  #define cmm_wmb()   asm volatile("lock; addl $0,0(%%esp)"::: "memory")
>  #endif
>  
> +/*
> + * An empty cmm_smp_rmb() may not be enough on old PentiumPro multiprocessor
> + * systems, due to an erratum, but the Linux kernel says that "Even distro
> + * kernels should think twice before enabling this".  Hence never generate
> + * code for it, even on machines that have no *fence instructions.
> + */
> +#define cmm_smp_rmb() cmm_barrier()

Can you leave this as a cmm_rmb() for now, so it does not break ppro ?
Then you can add configure options --without-x86-ppro-support and
--without-x86-idt-winchip-support to explicitly turn cmm_smp_rmb into a
simple compiler barrier and cmm_rmp_wmb into a simple compiler barrier.

Thanks,

Mathieu

> +
>  #define caa_cpu_relax()	asm volatile("rep; nop" : : : "memory");
>  
>  #define rdtscll(val)							  \
> -- 
> 1.7.6
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com

[ltt-dev] [URCU PATCH v2 1/2] caa: let per-arch files provide cmm_smp_* barriers

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> x86 instructions lfence and sfence are rarely needed, and we want
> the cmm_smp_rmb/cmm_smp_wmb macros to be simple compiler barriers.
> So, let the per-arch files override the default definitions in
> arch/generic.h.

Small nit: these 2 patches are named "caa:", but they should rather be
named "cmm:" (for Concurrent Memory Model).

Thanks!

Mathieu

> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch/generic.h |   28 ++++++++++++++++++++++++++++
>  1 files changed, 28 insertions(+), 0 deletions(-)
> 
> diff --git a/urcu/arch/generic.h b/urcu/arch/generic.h
> index 100d3c6..1ea7f59 100644
> --- a/urcu/arch/generic.h
> +++ b/urcu/arch/generic.h
> @@ -100,22 +100,50 @@ extern "C" {
>  #endif
>  
>  #ifdef CONFIG_RCU_SMP
> +#ifndef cmm_smp_mb
>  #define cmm_smp_mb()	cmm_mb()
> +#endif
> +#ifndef cmm_smp_rmb
>  #define cmm_smp_rmb()	cmm_rmb()
> +#endif
> +#ifndef cmm_smp_wmb
>  #define cmm_smp_wmb()	cmm_wmb()
> +#endif
> +#ifndef cmm_smp_mc
>  #define cmm_smp_mc()	cmm_mc()
> +#endif
> +#ifndef cmm_smp_rmc
>  #define cmm_smp_rmc()	cmm_rmc()
> +#endif
> +#ifndef cmm_smp_wmc
>  #define cmm_smp_wmc()	cmm_wmc()
> +#endif
> +#ifndef cmm_smp_read_barrier_depends
>  #define cmm_smp_read_barrier_depends()	cmm_read_barrier_depends()
> +#endif
>  #else
> +#ifndef cmm_smp_mb
>  #define cmm_smp_mb()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_rmb
>  #define cmm_smp_rmb()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_wmb
>  #define cmm_smp_wmb()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_mc
>  #define cmm_smp_mc()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_rmc
>  #define cmm_smp_rmc()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_wmc
>  #define cmm_smp_wmc()	cmm_barrier()
> +#endif
> +#ifndef cmm_smp_read_barrier_depends
>  #define cmm_smp_read_barrier_depends()
>  #endif
> +#endif
>  
>  #ifndef caa_cpu_relax
>  #define caa_cpu_relax()		cmm_barrier()
> -- 
> 1.7.6
> 
> 
> 
> _______________________________________________
> ltt-dev mailing list
> ltt-dev at lists.casi.polymtl.ca
> http://lists.casi.polymtl.ca/cgi-bin/mailman/listinfo/ltt-dev
> 

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com