[ltt-dev] [PATCH 0/4] Add gcc primitives, ia64 support, ARMv7L support, and kill unknown

[ltt-dev] [PATCH 0/4] Add gcc primitives, ia64 support, ARMv7L support, and kill unknown

[Paul E. McKenney]

Hello!

This set of four patches does the following:

o	Add header files providing definitions based on the gcc __sync_
	set of primitives.

o	Add IA64 support based on the gcc definitions.

o	Add native ARMv7L support.

o	Force build failures on unknown architectures.

							Thanx, Paul

 b/configure.ac                |    1 
 b/urcu/arch_armv7l.h          |   59 ++++++++++++++++++++++++++++++++++++++++++
 b/urcu/arch_gcc.h             |   59 ++++++++++++++++++++++++++++++++++++++++++
 b/urcu/arch_unknown.h         |   28 +++++++++++++++++++
 b/urcu/uatomic_arch_armv7l.h  |   48 ++++++++++++++++++++++++++++++++++
 b/urcu/uatomic_arch_gcc.h     |   48 ++++++++++++++++++++++++++++++++++
 b/urcu/uatomic_arch_unknown.h |   25 +++++++++++++++++
 configure.ac                  |   13 ++++-----
 8 files changed, 274 insertions(+), 7 deletions(-)

[ltt-dev] [PATCH 1/4] Add header files supporting gcc __sync_ primitives

[Paul E. McKenney]

Add a urcu/arch_gcc.h and urcu/uatomic_arch_gcc.h whose primitives are
based on the gcc __sync_ primitives.  This should be usable for all
systems that have correctly implemented __sync_ primitives, which sadly
does not include all combinations of systems and compilers.  In addition,
specific systems may gain higher performance with hand-coded primitives.
Nevertheless, this is nice for getting a new architecture up and running
quickly.

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
---
 urcu/arch_gcc.h         |   59 +++++++++++++++++++++++++++++++++++++++++++++++
 urcu/uatomic_arch_gcc.h |   48 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+), 0 deletions(-)
 create mode 100644 urcu/arch_gcc.h
 create mode 100644 urcu/uatomic_arch_gcc.h

diff --git a/urcu/arch_gcc.h b/urcu/arch_gcc.h
new file mode 100644
index 0000000..b625ae5
--- /dev/null
+++ b/urcu/arch_gcc.h
@@ -0,0 +1,59 @@
+#ifndef _URCU_ARCH_GCC_H
+#define _URCU_ARCH_GCC_H
+
+/*
+ * arch_unknown.h: trivial definitions for architectures using gcc __sync_
+ *
+ * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* We don't know, so guess!!! */
+#define CACHE_LINE_SIZE	128
+
+#define mb()    __sync_synchronize()
+
+#include <stdlib.h>
+#include <sys/time.h>
+
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+	cycles_t thetime;
+	struct timeval tv;
+
+	if (gettimeofday(&tv, NULL) != 0)
+		return 0;
+	thetime = ((cycles_t)tv.tv_sec) * 1000000ULL + ((cycles_t)tv.tv_usec);
+	return (cycles_t)thetime;
+}
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
+#endif /* _URCU_ARCH_GCC_H */
diff --git a/urcu/uatomic_arch_gcc.h b/urcu/uatomic_arch_gcc.h
new file mode 100644
index 0000000..df208bd
--- /dev/null
+++ b/urcu/uatomic_arch_gcc.h
@@ -0,0 +1,48 @@
+#ifndef _URCU_ARCH_UATOMIC_GCC_H
+#define _URCU_ARCH_UATOMIC_GCC_H
+
+/* 
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2009      Mathieu Desnoyers
+ * Copyright (c) 2010      Paul E. McKenney, IBM Corporation
+ *			   (Adapted from uatomic_arch_ppc.h)
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ *
+ * Code inspired from libuatomic_ops-1.2, inherited in part from the
+ * Boehm-Demers-Weiser conservative garbage collector.
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* xchg */
+#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
+
+/* cmpxchg */
+#define uatomic_cmpxchg(addr, old, _new) \
+	__sync_val_compare_and_swap(addr, old, _new)
+
+/* uatomic_add_return */
+#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/uatomic_generic.h>
+
+#endif /* _URCU_ARCH_UATOMIC_GCC_H */
-- 
1.7.0.6

[ltt-dev] [PATCH 2/4] Add ia64 architecture based on gcc primitives

[Paul E. McKenney]

This of course assumes that ia64 gcc correctly implements the various
__sync_ primitives.  ;-)

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
---
 configure.ac |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/configure.ac b/configure.ac
index 1b1ca65..61a0d76 100644
--- a/configure.ac
+++ b/configure.ac
@@ -51,6 +51,7 @@ case $host_cpu in
 	s390x) ARCHTYPE="s390" ;;
 	sparc64) ARCHTYPE="sparc64" ;;
 	alpha*) ARCHTYPE="alpha" ;;
+	ia64) ARCHTYPE="gcc" ;;
 	*) ARCHTYPE="unknown";;
 esac
 
-- 
1.7.0.6

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Paul E. McKenney]

Add native support for armv7l.  Other variants of ARM will likely require
separate ports.

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
---
 configure.ac               |    4 +++
 urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
 urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+), 0 deletions(-)
 create mode 100644 urcu/arch_armv7l.h
 create mode 100644 urcu/uatomic_arch_armv7l.h

diff --git a/configure.ac b/configure.ac
index 61a0d76..7b46004 100644
--- a/configure.ac
+++ b/configure.ac
@@ -52,6 +52,7 @@ case $host_cpu in
 	sparc64) ARCHTYPE="sparc64" ;;
 	alpha*) ARCHTYPE="alpha" ;;
 	ia64) ARCHTYPE="gcc" ;;
+	armv7l) ARCHTYPE="armv7l" ;;
 	*) ARCHTYPE="unknown";;
 esac
 
@@ -67,6 +68,9 @@ if test "x$ARCHTYPE" != xx86 -a "x$ARCHTYPE" != xppc; then
 else
 	APISRC=tests/api_$ARCHTYPE.h
 fi
+if test "$ARCHTYPE" == "armv7l"; then
+	CFLAGS="-mcpu=cortex-a9 -mtune=cortex-a9 -O"
+fi
 
 AC_SUBST(ARCHTYPE)
 AC_SUBST(SUBARCHTYPE)
diff --git a/urcu/arch_armv7l.h b/urcu/arch_armv7l.h
new file mode 100644
index 0000000..cfe05ef
--- /dev/null
+++ b/urcu/arch_armv7l.h
@@ -0,0 +1,59 @@
+#ifndef _URCU_ARCH_ARMV7L_H
+#define _URCU_ARCH_ARMV7L_H
+
+/*
+ * arch_armv7l.h: trivial definitions for the ARMv7 architecture.
+ *
+ * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* We don't know, so guess!!! */
+#define CACHE_LINE_SIZE	128
+
+#define mb()    asm volatile("dmb":::"memory")
+
+#include <stdlib.h>
+#include <sys/time.h>
+
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+	cycles_t thetime;
+	struct timeval tv;
+
+	if (gettimeofday(&tv, NULL) != 0)
+		return 0;
+	thetime = ((cycles_t)tv.tv_sec) * 1000000ULL + ((cycles_t)tv.tv_usec);
+	return (cycles_t)thetime;
+}
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
+#endif /* _URCU_ARCH_ARMV7L_H */
diff --git a/urcu/uatomic_arch_armv7l.h b/urcu/uatomic_arch_armv7l.h
new file mode 100644
index 0000000..19286c3
--- /dev/null
+++ b/urcu/uatomic_arch_armv7l.h
@@ -0,0 +1,48 @@
+#ifndef _URCU_ARCH_UATOMIC_ARMV7L_H
+#define _URCU_ARCH_UATOMIC_ARMV7L_H
+
+/* 
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2009      Mathieu Desnoyers
+ * Copyright (c) 2010      Paul E. McKenney, IBM Corporation
+ *			   (Adapted from uatomic_arch_ppc.h)
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ *
+ * Code inspired from libuatomic_ops-1.2, inherited in part from the
+ * Boehm-Demers-Weiser conservative garbage collector.
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* xchg */
+#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
+
+/* cmpxchg */
+#define uatomic_cmpxchg(addr, old, _new) \
+	__sync_val_compare_and_swap(addr, old, _new)
+
+/* uatomic_add_return */
+#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/uatomic_generic.h>
+
+#endif /* _URCU_ARCH_UATOMIC_ARMV7L_H */
-- 
1.7.0.6

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Mathieu Desnoyers]

* Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> Add native support for armv7l.  Other variants of ARM will likely require
> separate ports.
> 
> Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> ---
>  configure.ac               |    4 +++
>  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
>  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
>  3 files changed, 111 insertions(+), 0 deletions(-)
>  create mode 100644 urcu/arch_armv7l.h
>  create mode 100644 urcu/uatomic_arch_armv7l.h
> 
> diff --git a/configure.ac b/configure.ac
> index 61a0d76..7b46004 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -52,6 +52,7 @@ case $host_cpu in
>  	sparc64) ARCHTYPE="sparc64" ;;
>  	alpha*) ARCHTYPE="alpha" ;;
>  	ia64) ARCHTYPE="gcc" ;;
> +	armv7l) ARCHTYPE="armv7l" ;;
>  	*) ARCHTYPE="unknown";;
>  esac
>  
> @@ -67,6 +68,9 @@ if test "x$ARCHTYPE" != xx86 -a "x$ARCHTYPE" != xppc; then
>  else
>  	APISRC=tests/api_$ARCHTYPE.h
>  fi
> +if test "$ARCHTYPE" == "armv7l"; then
> +	CFLAGS="-mcpu=cortex-a9 -mtune=cortex-a9 -O"
> +fi
>  
>  AC_SUBST(ARCHTYPE)
>  AC_SUBST(SUBARCHTYPE)
> diff --git a/urcu/arch_armv7l.h b/urcu/arch_armv7l.h
> new file mode 100644
> index 0000000..cfe05ef
> --- /dev/null
> +++ b/urcu/arch_armv7l.h
> @@ -0,0 +1,59 @@
> +#ifndef _URCU_ARCH_ARMV7L_H
> +#define _URCU_ARCH_ARMV7L_H
> +
> +/*
> + * arch_armv7l.h: trivial definitions for the ARMv7 architecture.
> + *
> + * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
> + * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
> + */
> +
> +#include <urcu/compiler.h>
> +#include <urcu/config.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif 
> +
> +/* We don't know, so guess!!! */
> +#define CACHE_LINE_SIZE	128
> +
> +#define mb()    asm volatile("dmb":::"memory")
> +
> +#include <stdlib.h>
> +#include <sys/time.h>
> +
> +typedef unsigned long long cycles_t;
> +
> +static inline cycles_t get_cycles (void)
> +{
> +	cycles_t thetime;
> +	struct timeval tv;
> +
> +	if (gettimeofday(&tv, NULL) != 0)
> +		return 0;
> +	thetime = ((cycles_t)tv.tv_sec) * 1000000ULL + ((cycles_t)tv.tv_usec);
> +	return (cycles_t)thetime;
> +}
> +
> +#ifdef __cplusplus 
> +}
> +#endif
> +
> +#include <urcu/arch_generic.h>
> +
> +#endif /* _URCU_ARCH_ARMV7L_H */
> diff --git a/urcu/uatomic_arch_armv7l.h b/urcu/uatomic_arch_armv7l.h
> new file mode 100644
> index 0000000..19286c3
> --- /dev/null
> +++ b/urcu/uatomic_arch_armv7l.h
> @@ -0,0 +1,48 @@
> +#ifndef _URCU_ARCH_UATOMIC_ARMV7L_H
> +#define _URCU_ARCH_UATOMIC_ARMV7L_H
> +
> +/* 
> + * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
> + * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
> + * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
> + * Copyright (c) 2009      Mathieu Desnoyers
> + * Copyright (c) 2010      Paul E. McKenney, IBM Corporation
> + *			   (Adapted from uatomic_arch_ppc.h)
> + *
> + * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
> + * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
> + *
> + * Permission is hereby granted to use or copy this program
> + * for any purpose,  provided the above notices are retained on all copies.
> + * Permission to modify the code and to distribute modified code is granted,
> + * provided the above notices are retained, and a notice that the code was
> + * modified is included with the above copyright notice.
> + *
> + * Code inspired from libuatomic_ops-1.2, inherited in part from the
> + * Boehm-Demers-Weiser conservative garbage collector.
> + */
> +
> +#include <urcu/compiler.h>
> +#include <urcu/system.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif 
> +
> +/* xchg */
> +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> +
> +/* cmpxchg */
> +#define uatomic_cmpxchg(addr, old, _new) \
> +	__sync_val_compare_and_swap(addr, old, _new)
> +
> +/* uatomic_add_return */
> +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)

So, do we end up trusting that gcc got the memory barriers right in the ARM
__sync_() primitives ? That sounds unlikely.

I'd vote for surrounding these primitives with smp_mb().

Thanks,

Mathieu

> +
> +#ifdef __cplusplus 
> +}
> +#endif
> +
> +#include <urcu/uatomic_generic.h>
> +
> +#endif /* _URCU_ARCH_UATOMIC_ARMV7L_H */
> -- 
> 1.7.0.6
> 

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Paul E. McKenney]

On Wed, Jun 16, 2010 at 05:23:15PM -0400, Mathieu Desnoyers wrote:
> * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > Add native support for armv7l.  Other variants of ARM will likely require
> > separate ports.
> > 
> > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > ---
> >  configure.ac               |    4 +++
> >  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
> >  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++

[ . . . ]

> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif 
> > +
> > +/* xchg */
> > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > +
> > +/* cmpxchg */
> > +#define uatomic_cmpxchg(addr, old, _new) \
> > +	__sync_val_compare_and_swap(addr, old, _new)
> > +
> > +/* uatomic_add_return */
> > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> 
> So, do we end up trusting that gcc got the memory barriers right in the ARM
> __sync_() primitives ? That sounds unlikely.
> 
> I'd vote for surrounding these primitives with smp_mb().

On ARM, my current belief is that the primitives other than
__sync_synchronize() and __sync_lock_release() are set up correctly.

However, I must defer to Paolo and Uli on this.

							Thanx, Paul

> Thanks,
> 
> Mathieu
> 
> > +
> > +#ifdef __cplusplus 
> > +}
> > +#endif
> > +
> > +#include <urcu/uatomic_generic.h>
> > +
> > +#endif /* _URCU_ARCH_UATOMIC_ARMV7L_H */
> > -- 
> > 1.7.0.6
> > 
> 
> -- 
> Mathieu Desnoyers
> Operating System Efficiency R&D Consultant
> EfficiOS Inc.
> http://www.efficios.com

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Mathieu Desnoyers]

* Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> On Wed, Jun 16, 2010 at 05:23:15PM -0400, Mathieu Desnoyers wrote:
> > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > Add native support for armv7l.  Other variants of ARM will likely require
> > > separate ports.
> > > 
> > > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > > ---
> > >  configure.ac               |    4 +++
> > >  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
> > >  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
> 
> [ . . . ]
> 
> > > +#ifdef __cplusplus
> > > +extern "C" {
> > > +#endif 
> > > +
> > > +/* xchg */
> > > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > > +
> > > +/* cmpxchg */
> > > +#define uatomic_cmpxchg(addr, old, _new) \
> > > +	__sync_val_compare_and_swap(addr, old, _new)
> > > +
> > > +/* uatomic_add_return */
> > > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> > 
> > So, do we end up trusting that gcc got the memory barriers right in the ARM
> > __sync_() primitives ? That sounds unlikely.
> > 
> > I'd vote for surrounding these primitives with smp_mb().
> 
> On ARM, my current belief is that the primitives other than
> __sync_synchronize() and __sync_lock_release() are set up correctly.
> 
> However, I must defer to Paolo and Uli on this.

There is nothing like a quick test to see the result:

With a arm-linux-cs2009q1-203sb1 scratchbox compiler (gcc 4.3.3, provided by
Nokia for the Omap3):

arm-none-linux-gnueabi-gcc-4.3.3 (Sourcery G++ Lite 2009q1-203) 4.3.3

I compile, with

/scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-gcc-4.3.3 -mcpu=cortex-a9 -mtune=cortex-a9 -O2 -o armtest armtest.c

the following program:

int a;

int
f()
{
        __sync_val_compare_and_swap(&a, 4, 1);
        //__sync_lock_test_and_set(&a, 1);
        //__sync_add_and_fetch(&a, 1);
        //__sync_synchronize();
}

int main()
{
        f();
}

and get:

/scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-objdump -S armtest

[...]


000083cc <f>:
    83cc:       e59f0008        ldr     r0, [pc, #8]    ; 83dc <f+0x10>
    83d0:       e3a01004        mov     r1, #4  ; 0x4
    83d4:       e3a02001        mov     r2, #1  ; 0x1
    83d8:       ea000305        b       8ff4 <__sync_val_compare_and_swap_4>
    83dc:       00011524        .word   0x00011524

[...]

00008ff4 <__sync_val_compare_and_swap_4>:
    8ff4:       e92d41f0        push    {r4, r5, r6, r7, r8, lr}
    8ff8:       e59f8034        ldr     r8, [pc, #52]   ; 9034 <__sync_val_compare_and_swap_4+0x40>
    8ffc:       e1a06000        mov     r6, r0
    9000:       e1a05001        mov     r5, r1
    9004:       e1a07002        mov     r7, r2
    9008:       e5964000        ldr     r4, [r6]
    900c:       e1a00005        mov     r0, r5
    9010:       e1550004        cmp     r5, r4
    9014:       e1a01007        mov     r1, r7
    9018:       e1a02006        mov     r2, r6
    901c:       1a000002        bne     902c <__sync_val_compare_and_swap_4+0x38>
    9020:       e12fff38        blx     r8
    9024:       e3500000        cmp     r0, #0  ; 0x0
    9028:       1afffff6        bne     9008 <__sync_val_compare_and_swap_4+0x14>
    902c:       e1a00004        mov     r0, r4
    9030:       e8bd81f0        pop     {r4, r5, r6, r7, r8, pc}
    9034:       ffff0fc0        .word   0xffff0fc0

Where sadly the appropriate memory barriers are missing, and even the
appropriate ldrex/teq, strexeq sequence is missing. So not only is this
incorrect in terms of memory barriers, but also in terms of atomicity. Argh. I
don't know if a compiler more recent than 4.3.3 would do better though, but I
start to think that it would be wise to stay far away from gcc __sync_*()
primitives. For ARM at least.

Thanks,

Mathieu


> 
> > Thanks,
> > 
> > Mathieu
> > 
> > > +
> > > +#ifdef __cplusplus 
> > > +}
> > > +#endif
> > > +
> > > +#include <urcu/uatomic_generic.h>
> > > +
> > > +#endif /* _URCU_ARCH_UATOMIC_ARMV7L_H */
> > > -- 
> > > 1.7.0.6
> > > 
> > 
> > -- 
> > Mathieu Desnoyers
> > Operating System Efficiency R&D Consultant
> > EfficiOS Inc.
> > http://www.efficios.com

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Paul E. McKenney]

On Wed, Jun 16, 2010 at 07:57:55PM -0400, Mathieu Desnoyers wrote:
> * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > On Wed, Jun 16, 2010 at 05:23:15PM -0400, Mathieu Desnoyers wrote:
> > > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > > Add native support for armv7l.  Other variants of ARM will likely require
> > > > separate ports.
> > > > 
> > > > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > > > ---
> > > >  configure.ac               |    4 +++
> > > >  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
> > > >  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
> > 
> > [ . . . ]
> > 
> > > > +#ifdef __cplusplus
> > > > +extern "C" {
> > > > +#endif 
> > > > +
> > > > +/* xchg */
> > > > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > > > +
> > > > +/* cmpxchg */
> > > > +#define uatomic_cmpxchg(addr, old, _new) \
> > > > +	__sync_val_compare_and_swap(addr, old, _new)
> > > > +
> > > > +/* uatomic_add_return */
> > > > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> > > 
> > > So, do we end up trusting that gcc got the memory barriers right in the ARM
> > > __sync_() primitives ? That sounds unlikely.
> > > 
> > > I'd vote for surrounding these primitives with smp_mb().
> > 
> > On ARM, my current belief is that the primitives other than
> > __sync_synchronize() and __sync_lock_release() are set up correctly.
> > 
> > However, I must defer to Paolo and Uli on this.
> 
> There is nothing like a quick test to see the result:
> 
> With a arm-linux-cs2009q1-203sb1 scratchbox compiler (gcc 4.3.3, provided by
> Nokia for the Omap3):
> 
> arm-none-linux-gnueabi-gcc-4.3.3 (Sourcery G++ Lite 2009q1-203) 4.3.3
> 
> I compile, with
> 
> /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-gcc-4.3.3 -mcpu=cortex-a9 -mtune=cortex-a9 -O2 -o armtest armtest.c
> 
> the following program:
> 
> int a;
> 
> int
> f()
> {
>         __sync_val_compare_and_swap(&a, 4, 1);
>         //__sync_lock_test_and_set(&a, 1);
>         //__sync_add_and_fetch(&a, 1);
>         //__sync_synchronize();
> }
> 
> int main()
> {
>         f();
> }
> 
> and get:
> 
> /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-objdump -S armtest
> 
> [...]
> 
> 
> 000083cc <f>:
>     83cc:       e59f0008        ldr     r0, [pc, #8]    ; 83dc <f+0x10>
>     83d0:       e3a01004        mov     r1, #4  ; 0x4
>     83d4:       e3a02001        mov     r2, #1  ; 0x1
>     83d8:       ea000305        b       8ff4 <__sync_val_compare_and_swap_4>
>     83dc:       00011524        .word   0x00011524
> 
> [...]
> 
> 00008ff4 <__sync_val_compare_and_swap_4>:
>     8ff4:       e92d41f0        push    {r4, r5, r6, r7, r8, lr}
>     8ff8:       e59f8034        ldr     r8, [pc, #52]   ; 9034 <__sync_val_compare_and_swap_4+0x40>
>     8ffc:       e1a06000        mov     r6, r0
>     9000:       e1a05001        mov     r5, r1
>     9004:       e1a07002        mov     r7, r2
>     9008:       e5964000        ldr     r4, [r6]
>     900c:       e1a00005        mov     r0, r5
>     9010:       e1550004        cmp     r5, r4
>     9014:       e1a01007        mov     r1, r7
>     9018:       e1a02006        mov     r2, r6
>     901c:       1a000002        bne     902c <__sync_val_compare_and_swap_4+0x38>
>     9020:       e12fff38        blx     r8
>     9024:       e3500000        cmp     r0, #0  ; 0x0
>     9028:       1afffff6        bne     9008 <__sync_val_compare_and_swap_4+0x14>
>     902c:       e1a00004        mov     r0, r4
>     9030:       e8bd81f0        pop     {r4, r5, r6, r7, r8, pc}
>     9034:       ffff0fc0        .word   0xffff0fc0
> 
> Where sadly the appropriate memory barriers are missing, and even the
> appropriate ldrex/teq, strexeq sequence is missing. So not only is this
> incorrect in terms of memory barriers, but also in terms of atomicity. Argh. I
> don't know if a compiler more recent than 4.3.3 would do better though, but I
> start to think that it would be wise to stay far away from gcc __sync_*()
> primitives. For ARM at least.

The way it was explained to me is that the "blx r8" above branches to a
code page supplied by the kernel, and that this page contains the memory
barriers and atomic instructions.  The "x" in the "blx" switches from
ARM to Thumb instruction-set format, just to keep things interesting.

The address is 0xffff0fc0, the value at address 0x9035 above.  Naturally,
gdb refuses to let me look at this address range.  My attempt to access
this range from inside the program also fails.  Which is not a surprise,
it is not supposed to be mapped.  Assuming you have a multicore ARMv6
or later, the kernel supplies the following code at this address (see
arch/arm/kernel/entry-armv.S):

		smp_dmb
	1:	ldrex	r3, [r2]
		subs	r3, r3, r0
		strexeq	r3, r1, [r2]
		teqeq	r3, #1
		beq	1b
		rsbs	r0, r3, #0
		/* beware -- each __kuser slot must be 8 instructions max */
	#ifdef CONFIG_SMP
		b	__kuser_memory_barrier
	#else
		usr_ret	lr
	#endif

The smp_dmb is an assembler macro (haven't come across one of those for
like 30 years!!!) that expands to different things depending on the ARM
architecture level that the kernel is built for.  The ldrex and strexeq
are ARM's atomic instructions, sort of like larx/stcx on ppc.

This is admittedly a bit involuted, but the really nice thing about it
is that it works on a wider variety of ARM architectures.

This approach OK for you?

							Thanx, Paul

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Mathieu Desnoyers]

* Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> On Wed, Jun 16, 2010 at 07:57:55PM -0400, Mathieu Desnoyers wrote:
> > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > On Wed, Jun 16, 2010 at 05:23:15PM -0400, Mathieu Desnoyers wrote:
> > > > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > > > Add native support for armv7l.  Other variants of ARM will likely require
> > > > > separate ports.
> > > > > 
> > > > > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > > > > ---
> > > > >  configure.ac               |    4 +++
> > > > >  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
> > > > >  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
> > > 
> > > [ . . . ]
> > > 
> > > > > +#ifdef __cplusplus
> > > > > +extern "C" {
> > > > > +#endif 
> > > > > +
> > > > > +/* xchg */
> > > > > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > > > > +
> > > > > +/* cmpxchg */
> > > > > +#define uatomic_cmpxchg(addr, old, _new) \
> > > > > +	__sync_val_compare_and_swap(addr, old, _new)
> > > > > +
> > > > > +/* uatomic_add_return */
> > > > > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> > > > 
> > > > So, do we end up trusting that gcc got the memory barriers right in the ARM
> > > > __sync_() primitives ? That sounds unlikely.
> > > > 
> > > > I'd vote for surrounding these primitives with smp_mb().
> > > 
> > > On ARM, my current belief is that the primitives other than
> > > __sync_synchronize() and __sync_lock_release() are set up correctly.
> > > 
> > > However, I must defer to Paolo and Uli on this.
> > 
> > There is nothing like a quick test to see the result:
> > 
> > With a arm-linux-cs2009q1-203sb1 scratchbox compiler (gcc 4.3.3, provided by
> > Nokia for the Omap3):
> > 
> > arm-none-linux-gnueabi-gcc-4.3.3 (Sourcery G++ Lite 2009q1-203) 4.3.3
> > 
> > I compile, with
> > 
> > /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-gcc-4.3.3 -mcpu=cortex-a9 -mtune=cortex-a9 -O2 -o armtest armtest.c
> > 
> > the following program:
> > 
> > int a;
> > 
> > int
> > f()
> > {
> >         __sync_val_compare_and_swap(&a, 4, 1);
> >         //__sync_lock_test_and_set(&a, 1);
> >         //__sync_add_and_fetch(&a, 1);
> >         //__sync_synchronize();
> > }
> > 
> > int main()
> > {
> >         f();
> > }
> > 
> > and get:
> > 
> > /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-objdump -S armtest
> > 
> > [...]
> > 
> > 
> > 000083cc <f>:
> >     83cc:       e59f0008        ldr     r0, [pc, #8]    ; 83dc <f+0x10>
> >     83d0:       e3a01004        mov     r1, #4  ; 0x4
> >     83d4:       e3a02001        mov     r2, #1  ; 0x1
> >     83d8:       ea000305        b       8ff4 <__sync_val_compare_and_swap_4>
> >     83dc:       00011524        .word   0x00011524
> > 
> > [...]
> > 
> > 00008ff4 <__sync_val_compare_and_swap_4>:
> >     8ff4:       e92d41f0        push    {r4, r5, r6, r7, r8, lr}
> >     8ff8:       e59f8034        ldr     r8, [pc, #52]   ; 9034 <__sync_val_compare_and_swap_4+0x40>
> >     8ffc:       e1a06000        mov     r6, r0
> >     9000:       e1a05001        mov     r5, r1
> >     9004:       e1a07002        mov     r7, r2
> >     9008:       e5964000        ldr     r4, [r6]
> >     900c:       e1a00005        mov     r0, r5
> >     9010:       e1550004        cmp     r5, r4
> >     9014:       e1a01007        mov     r1, r7
> >     9018:       e1a02006        mov     r2, r6
> >     901c:       1a000002        bne     902c <__sync_val_compare_and_swap_4+0x38>
> >     9020:       e12fff38        blx     r8
> >     9024:       e3500000        cmp     r0, #0  ; 0x0
> >     9028:       1afffff6        bne     9008 <__sync_val_compare_and_swap_4+0x14>
> >     902c:       e1a00004        mov     r0, r4
> >     9030:       e8bd81f0        pop     {r4, r5, r6, r7, r8, pc}
> >     9034:       ffff0fc0        .word   0xffff0fc0
> > 
> > Where sadly the appropriate memory barriers are missing, and even the
> > appropriate ldrex/teq, strexeq sequence is missing. So not only is this
> > incorrect in terms of memory barriers, but also in terms of atomicity. Argh. I
> > don't know if a compiler more recent than 4.3.3 would do better though, but I
> > start to think that it would be wise to stay far away from gcc __sync_*()
> > primitives. For ARM at least.
> 
> The way it was explained to me is that the "blx r8" above branches to a
> code page supplied by the kernel, and that this page contains the memory
> barriers and atomic instructions.  The "x" in the "blx" switches from
> ARM to Thumb instruction-set format, just to keep things interesting.
> 
> The address is 0xffff0fc0, the value at address 0x9035 above.  Naturally,
> gdb refuses to let me look at this address range.  My attempt to access
> this range from inside the program also fails.  Which is not a surprise,
> it is not supposed to be mapped.  Assuming you have a multicore ARMv6
> or later, the kernel supplies the following code at this address (see
> arch/arm/kernel/entry-armv.S):
> 
> 		smp_dmb
> 	1:	ldrex	r3, [r2]
> 		subs	r3, r3, r0
> 		strexeq	r3, r1, [r2]
> 		teqeq	r3, #1
> 		beq	1b
> 		rsbs	r0, r3, #0
> 		/* beware -- each __kuser slot must be 8 instructions max */
> 	#ifdef CONFIG_SMP
> 		b	__kuser_memory_barrier
> 	#else
> 		usr_ret	lr
> 	#endif
> 
> The smp_dmb is an assembler macro (haven't come across one of those for
> like 30 years!!!) that expands to different things depending on the ARM
> architecture level that the kernel is built for.  The ldrex and strexeq
> are ARM's atomic instructions, sort of like larx/stcx on ppc.
> 
> This is admittedly a bit involuted, but the really nice thing about it
> is that it works on a wider variety of ARM architectures.
> 
> This approach OK for you?

Yep, sounds fine :) I wonder if we could document how far back we expect ARM
Linux kernels to work (e.g. not earlier than 2.6.15). I guess this in-kernel
cmpxchg has not been there forever.

Thanks,

Mathieu


-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Paul E. McKenney]

On Wed, Jun 16, 2010 at 09:37:02PM -0400, Mathieu Desnoyers wrote:
> * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > On Wed, Jun 16, 2010 at 07:57:55PM -0400, Mathieu Desnoyers wrote:
> > > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > > On Wed, Jun 16, 2010 at 05:23:15PM -0400, Mathieu Desnoyers wrote:
> > > > > * Paul E. McKenney (paulmck at linux.vnet.ibm.com) wrote:
> > > > > > Add native support for armv7l.  Other variants of ARM will likely require
> > > > > > separate ports.
> > > > > > 
> > > > > > Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
> > > > > > ---
> > > > > >  configure.ac               |    4 +++
> > > > > >  urcu/arch_armv7l.h         |   59 ++++++++++++++++++++++++++++++++++++++++++++
> > > > > >  urcu/uatomic_arch_armv7l.h |   48 +++++++++++++++++++++++++++++++++++
> > > > 
> > > > [ . . . ]
> > > > 
> > > > > > +#ifdef __cplusplus
> > > > > > +extern "C" {
> > > > > > +#endif 
> > > > > > +
> > > > > > +/* xchg */
> > > > > > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > > > > > +
> > > > > > +/* cmpxchg */
> > > > > > +#define uatomic_cmpxchg(addr, old, _new) \
> > > > > > +	__sync_val_compare_and_swap(addr, old, _new)
> > > > > > +
> > > > > > +/* uatomic_add_return */
> > > > > > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> > > > > 
> > > > > So, do we end up trusting that gcc got the memory barriers right in the ARM
> > > > > __sync_() primitives ? That sounds unlikely.
> > > > > 
> > > > > I'd vote for surrounding these primitives with smp_mb().
> > > > 
> > > > On ARM, my current belief is that the primitives other than
> > > > __sync_synchronize() and __sync_lock_release() are set up correctly.
> > > > 
> > > > However, I must defer to Paolo and Uli on this.
> > > 
> > > There is nothing like a quick test to see the result:
> > > 
> > > With a arm-linux-cs2009q1-203sb1 scratchbox compiler (gcc 4.3.3, provided by
> > > Nokia for the Omap3):
> > > 
> > > arm-none-linux-gnueabi-gcc-4.3.3 (Sourcery G++ Lite 2009q1-203) 4.3.3
> > > 
> > > I compile, with
> > > 
> > > /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-gcc-4.3.3 -mcpu=cortex-a9 -mtune=cortex-a9 -O2 -o armtest armtest.c
> > > 
> > > the following program:
> > > 
> > > int a;
> > > 
> > > int
> > > f()
> > > {
> > >         __sync_val_compare_and_swap(&a, 4, 1);
> > >         //__sync_lock_test_and_set(&a, 1);
> > >         //__sync_add_and_fetch(&a, 1);
> > >         //__sync_synchronize();
> > > }
> > > 
> > > int main()
> > > {
> > >         f();
> > > }
> > > 
> > > and get:
> > > 
> > > /scratchbox/compilers/arm-linux-cs2009q1-203sb1/bin/arm-none-linux-gnueabi-objdump -S armtest
> > > 
> > > [...]
> > > 
> > > 
> > > 000083cc <f>:
> > >     83cc:       e59f0008        ldr     r0, [pc, #8]    ; 83dc <f+0x10>
> > >     83d0:       e3a01004        mov     r1, #4  ; 0x4
> > >     83d4:       e3a02001        mov     r2, #1  ; 0x1
> > >     83d8:       ea000305        b       8ff4 <__sync_val_compare_and_swap_4>
> > >     83dc:       00011524        .word   0x00011524
> > > 
> > > [...]
> > > 
> > > 00008ff4 <__sync_val_compare_and_swap_4>:
> > >     8ff4:       e92d41f0        push    {r4, r5, r6, r7, r8, lr}
> > >     8ff8:       e59f8034        ldr     r8, [pc, #52]   ; 9034 <__sync_val_compare_and_swap_4+0x40>
> > >     8ffc:       e1a06000        mov     r6, r0
> > >     9000:       e1a05001        mov     r5, r1
> > >     9004:       e1a07002        mov     r7, r2
> > >     9008:       e5964000        ldr     r4, [r6]
> > >     900c:       e1a00005        mov     r0, r5
> > >     9010:       e1550004        cmp     r5, r4
> > >     9014:       e1a01007        mov     r1, r7
> > >     9018:       e1a02006        mov     r2, r6
> > >     901c:       1a000002        bne     902c <__sync_val_compare_and_swap_4+0x38>
> > >     9020:       e12fff38        blx     r8
> > >     9024:       e3500000        cmp     r0, #0  ; 0x0
> > >     9028:       1afffff6        bne     9008 <__sync_val_compare_and_swap_4+0x14>
> > >     902c:       e1a00004        mov     r0, r4
> > >     9030:       e8bd81f0        pop     {r4, r5, r6, r7, r8, pc}
> > >     9034:       ffff0fc0        .word   0xffff0fc0
> > > 
> > > Where sadly the appropriate memory barriers are missing, and even the
> > > appropriate ldrex/teq, strexeq sequence is missing. So not only is this
> > > incorrect in terms of memory barriers, but also in terms of atomicity. Argh. I
> > > don't know if a compiler more recent than 4.3.3 would do better though, but I
> > > start to think that it would be wise to stay far away from gcc __sync_*()
> > > primitives. For ARM at least.
> > 
> > The way it was explained to me is that the "blx r8" above branches to a
> > code page supplied by the kernel, and that this page contains the memory
> > barriers and atomic instructions.  The "x" in the "blx" switches from
> > ARM to Thumb instruction-set format, just to keep things interesting.
> > 
> > The address is 0xffff0fc0, the value at address 0x9035 above.  Naturally,
> > gdb refuses to let me look at this address range.  My attempt to access
> > this range from inside the program also fails.  Which is not a surprise,
> > it is not supposed to be mapped.  Assuming you have a multicore ARMv6
> > or later, the kernel supplies the following code at this address (see
> > arch/arm/kernel/entry-armv.S):
> > 
> > 		smp_dmb
> > 	1:	ldrex	r3, [r2]
> > 		subs	r3, r3, r0
> > 		strexeq	r3, r1, [r2]
> > 		teqeq	r3, #1
> > 		beq	1b
> > 		rsbs	r0, r3, #0
> > 		/* beware -- each __kuser slot must be 8 instructions max */
> > 	#ifdef CONFIG_SMP
> > 		b	__kuser_memory_barrier
> > 	#else
> > 		usr_ret	lr
> > 	#endif
> > 
> > The smp_dmb is an assembler macro (haven't come across one of those for
> > like 30 years!!!) that expands to different things depending on the ARM
> > architecture level that the kernel is built for.  The ldrex and strexeq
> > are ARM's atomic instructions, sort of like larx/stcx on ppc.
> > 
> > This is admittedly a bit involuted, but the really nice thing about it
> > is that it works on a wider variety of ARM architectures.
> > 
> > This approach OK for you?
> 
> Yep, sounds fine :) I wonder if we could document how far back we expect ARM
> Linux kernels to work (e.g. not earlier than 2.6.15). I guess this in-kernel
> cmpxchg has not been there forever.

OK, updating comments and commit message and reposting.

							Thanx, Paul

[ltt-dev] [PATCH 4/4] Force build failure on unknown architectures

[Paul E. McKenney]

Create urcu/arch_unknown.h and urcu/uatomic_arch_unknown.h, which
contain only #error statements and explanatory comments.  This forces
build failures on unrecognized architectures in preference to trying
to guess at what operations might be safe on such architectures.

One other semi-feasible alternative is to use hashed arrays of locks
that are acquired with signals disabled.  However, this seems a bit
too ornate, especially for architectures for which the gcc __sync_
primitives work correctly.

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
---
 configure.ac                |    9 ++-------
 urcu/arch_unknown.h         |   28 ++++++++++++++++++++++++++++
 urcu/uatomic_arch_unknown.h |   25 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 7 deletions(-)
 create mode 100644 urcu/arch_unknown.h
 create mode 100644 urcu/uatomic_arch_unknown.h

diff --git a/configure.ac b/configure.ac
index 7b46004..4daf3ba 100644
--- a/configure.ac
+++ b/configure.ac
@@ -56,13 +56,8 @@ case $host_cpu in
 	*) ARCHTYPE="unknown";;
 esac
 
-if test "$ARCHTYPE" != "unknown"; then
-	UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
-	ARCHSRC=urcu/arch_$ARCHTYPE.h
-else
-	UATOMICSRC=urcu/uatomic_generic.h
-	ARCHSRC=urcu/arch_generic.h
-fi
+UATOMICSRC=urcu/uatomic_arch_$ARCHTYPE.h
+ARCHSRC=urcu/arch_$ARCHTYPE.h
 if test "x$ARCHTYPE" != xx86 -a "x$ARCHTYPE" != xppc; then
 	APISRC=tests/api_gcc.h
 else
diff --git a/urcu/arch_unknown.h b/urcu/arch_unknown.h
new file mode 100644
index 0000000..2de6a6b
--- /dev/null
+++ b/urcu/arch_unknown.h
@@ -0,0 +1,28 @@
+#ifndef _URCU_ARCH_UNKNOWN_H
+#define _URCU_ARCH_UNKNOWN_H
+
+/*
+ * arch_unknown.h: #error to prevent build on unknown architectures.
+ *
+ * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* See configure.ac for the list of recognized architectures.  */
+#error "Cannot build: unrecognized architecture detected."
+
+#endif /* _URCU_ARCH_UNKNOWN_H */
diff --git a/urcu/uatomic_arch_unknown.h b/urcu/uatomic_arch_unknown.h
new file mode 100644
index 0000000..6fb4eb3
--- /dev/null
+++ b/urcu/uatomic_arch_unknown.h
@@ -0,0 +1,25 @@
+#ifndef _URCU_ARCH_UATOMIC_UNKNOWN_H
+#define _URCU_ARCH_UATOMIC_UNKNOWN_H
+
+/* 
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2009      Mathieu Desnoyers
+ * Copyright (c) 2010      Paul E. McKenney, IBM Corporation
+ *			   (Adapted from uatomic_arch_ppc.h)
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ */
+
+/* See configure.ac for the list of recognized architectures.  */
+#error "Cannot build: unrecognized architecture detected."
+
+#endif /* _URCU_ARCH_UATOMIC_UNKNOWN_H */
-- 
1.7.0.6

[ltt-dev] [PATCH 0/4] v3: Add gcc primitives, ia64 support, ARMv7L support, and kill unknown

[Paul E. McKenney]

Hello!

This set of four patches does the following:

o	Add header files providing definitions based on the gcc __sync_
	set of primitives.

o	Add IA64 support based on the gcc definitions.

o	Add native ARMv7L support.

o	Force build failures on unknown architectures.

Updates since v2:

o	Apply Paolo's feedback to avoid redundant code.

Updates since v1:

o	Add note that this works back to at least 2.6.15 kernels.

							Thanx, Paul

 b/configure.ac                |    1 
 b/urcu/arch_armv7l.h          |   56 ++++++++++++++++++++++++++++++++++++++++++
 b/urcu/arch_gcc.h             |   54 ++++++++++++++++++++++++++++++++++++++++
 b/urcu/arch_unknown.h         |   28 +++++++++++++++++++++
 b/urcu/uatomic_arch_armv7l.h  |   50 +++++++++++++++++++++++++++++++++++++
 b/urcu/uatomic_arch_gcc.h     |   46 ++++++++++++++++++++++++++++++++++
 b/urcu/uatomic_arch_unknown.h |   25 ++++++++++++++++++
 configure.ac                  |   13 ++++-----
 8 files changed, 266 insertions(+), 7 deletions(-)

[ltt-dev] [PATCH 3/4] Add native ARM port for armv7l

[Paul E. McKenney]

Add native support for armv7l.  Other variants of ARM will likely require
separate ports.  The gcc __sync_ approach works back to at least 2.6.15
kernels.

As suggested by Paolo Bonzini, defer the definition of CACHE_LINE_SIZE
to arch_generic.h.

Signed-off-by: Paul E. McKenney <paulmck at linux.vnet.ibm.com>
---
 configure.ac               |    4 +++
 urcu/arch_armv7l.h         |   56 ++++++++++++++++++++++++++++++++++++++++++++
 urcu/uatomic_arch_armv7l.h |   50 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 110 insertions(+), 0 deletions(-)
 create mode 100644 urcu/arch_armv7l.h
 create mode 100644 urcu/uatomic_arch_armv7l.h

diff --git a/configure.ac b/configure.ac
index 61a0d76..7b46004 100644
--- a/configure.ac
+++ b/configure.ac
@@ -52,6 +52,7 @@ case $host_cpu in
 	sparc64) ARCHTYPE="sparc64" ;;
 	alpha*) ARCHTYPE="alpha" ;;
 	ia64) ARCHTYPE="gcc" ;;
+	armv7l) ARCHTYPE="armv7l" ;;
 	*) ARCHTYPE="unknown";;
 esac
 
@@ -67,6 +68,9 @@ if test "x$ARCHTYPE" != xx86 -a "x$ARCHTYPE" != xppc; then
 else
 	APISRC=tests/api_$ARCHTYPE.h
 fi
+if test "$ARCHTYPE" == "armv7l"; then
+	CFLAGS="-mcpu=cortex-a9 -mtune=cortex-a9 -O"
+fi
 
 AC_SUBST(ARCHTYPE)
 AC_SUBST(SUBARCHTYPE)
diff --git a/urcu/arch_armv7l.h b/urcu/arch_armv7l.h
new file mode 100644
index 0000000..b4049cd
--- /dev/null
+++ b/urcu/arch_armv7l.h
@@ -0,0 +1,56 @@
+#ifndef _URCU_ARCH_ARMV7L_H
+#define _URCU_ARCH_ARMV7L_H
+
+/*
+ * arch_armv7l.h: trivial definitions for the ARMv7 architecture.
+ *
+ * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
+ * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at polymtl.ca>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#define mb()    asm volatile("dmb":::"memory")
+
+#include <stdlib.h>
+#include <sys/time.h>
+
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+	cycles_t thetime;
+	struct timeval tv;
+
+	if (gettimeofday(&tv, NULL) != 0)
+		return 0;
+	thetime = ((cycles_t)tv.tv_sec) * 1000000ULL + ((cycles_t)tv.tv_usec);
+	return (cycles_t)thetime;
+}
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/arch_generic.h>
+
+#endif /* _URCU_ARCH_ARMV7L_H */
diff --git a/urcu/uatomic_arch_armv7l.h b/urcu/uatomic_arch_armv7l.h
new file mode 100644
index 0000000..b68c818
--- /dev/null
+++ b/urcu/uatomic_arch_armv7l.h
@@ -0,0 +1,50 @@
+#ifndef _URCU_ARCH_UATOMIC_ARMV7L_H
+#define _URCU_ARCH_UATOMIC_ARMV7L_H
+
+/* 
+ * Atomics for ARMv7.  This approach is usable on kernels back to 2.6.15.
+ *
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2009      Mathieu Desnoyers
+ * Copyright (c) 2010      Paul E. McKenney, IBM Corporation
+ *			   (Adapted from uatomic_arch_ppc.h)
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ *
+ * Code inspired from libuatomic_ops-1.2, inherited in part from the
+ * Boehm-Demers-Weiser conservative garbage collector.
+ */
+
+#include <urcu/compiler.h>
+#include <urcu/system.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* xchg */
+#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
+
+/* cmpxchg */
+#define uatomic_cmpxchg(addr, old, _new) \
+	__sync_val_compare_and_swap(addr, old, _new)
+
+/* uatomic_add_return */
+#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
+
+#ifdef __cplusplus 
+}
+#endif
+
+#include <urcu/uatomic_generic.h>
+
+#endif /* _URCU_ARCH_UATOMIC_ARMV7L_H */
-- 
1.7.0.6