[ltt-dev] PMC support for ARMv6

[ltt-dev] PMC support for ARMv6

[Gaurav Singh]

Hi Mathieu / all,
I have integrated PMC in ARMv6 primarily for 2 aims:
1. CPI calculations - this trace_mark is triggered triggered after X no. of
clock cycles. The number of instructions executed and the no. of clock
cycles is noted.
2. Cache Hit rate calculation - Here I have not used the PMC registers in
the ARM processor - rather have used L2 Cache controller  registers to find
out this information - but this does not provide information about the L1
cache hit/miss behaviour.

Any other suggestions on what else can be done in PMC?

Also have ported LTTng to 2.6.24 for two Nomadik Boards - NDK15 and
NDK20. Doing some tests and will send it over to you guys soon for your
comments.

Cheers!
Have a Nice Day!
Gaurav
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[ltt-dev] PMC support for ARMv6

[Gaurav Singh]

Hi Mathieu / all,
I have integrated PMC in ARMv6 primarily for 2 aims:
1. CPI calculations - this trace_mark is triggered triggered after X no. of
clock cycles. The number of instructions executed and the no. of clock
cycles is noted.
2. Cache Hit rate calculation - Here I have not used the PMC registers in
the ARM processor - rather have used L2 Cache controller  registers to find
out this information - but this does not provide information about the L1
cache hit/miss behaviour.

Any other suggestions on what else can be done in PMC?

Also have ported LTTng to 2.6.24 for two Nomadik Boards - NDK15 and
NDK20. Doing some tests and will send it over to you guys soon for your
comments.

Cheers!
Have a Nice Day!
Gaurav
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[ltt-dev] PMC support for ARMv6

[Gaurav Singh]

Hi Mathieu / all,
I have integrated PMC in ARMv6 primarily for 2 aims:
1. CPI calculations - this trace_mark is triggered triggered after X no. of
clock cycles. The number of instructions executed and the no. of clock
cycles is noted.
2. Cache Hit rate calculation - Here I have not used the PMC registers in
the ARM processor - rather have used L2 Cache controller  registers to find
out this information - but this does not provide information about the L1
cache hit/miss behaviour.

Any other suggestions on what else can be done in PMC?

Also have ported LTTng to 2.6.24 for two Nomadik Boards - NDK15 and
NDK20. Doing some tests and will send it over to you guys soon for your
comments.

Cheers!
Have a Nice Day!
Gaurav
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[ltt-dev] PMC support for ARMv6

[Mathieu Desnoyers]

* Gaurav Singh (gausinghnsit at gmail.com) wrote:
> Hi Mathieu / all,
> I have integrated PMC in ARMv6 primarily for 2 aims:
> 1. CPI calculations - this trace_mark is triggered triggered after X no. of
> clock cycles. The number of instructions executed and the no. of clock
> cycles is noted.
> 2. Cache Hit rate calculation - Here I have not used the PMC registers in
> the ARM processor - rather have used L2 Cache controller  registers to find
> out this information - but this does not provide information about the L1
> cache hit/miss behaviour.
> 
> Any other suggestions on what else can be done in PMC?
> 

I'd like to see this trace_mark turned into a tracepoint probe. Having a
periodical interrupt which saves this information is good, but I would
also like to have a tracepoint probe that we could attach at important
execution sites, like sched change, irq, softirq, nmi entry/exit where
we would read the performance counter.


> Also have ported LTTng to 2.6.24 for two Nomadik Boards - NDK15 and
> NDK20. Doing some tests and will send it over to you guys soon for your
> comments.
> 

I'd be interested in merging your patchesfor 2.6.28 into the LTTng tree.
Please keep us posted.

Mathieu

> Cheers!
> Have a Nice Day!
> Gaurav

-- 
Mathieu Desnoyers
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