Re: can target code change architecture setting?

[Yao Qi <qiyaoltc@gmail.com>]

On Fri, Oct 7, 2016 at 6:38 PM, Tim Newsome <tim@sifive.com> wrote:
> I’m working with riscv gdb support. One problem people occasionally
> run into is that riscv has both 32- and 64-bit variants. The current
> gdb code just assumes 64-bit by default (unless a file is specified,
> and then it gets the info from the ELF info). If such a gdb connects
> to a 32-bit target, bulk register reads end up wonky, and writes send
> too much data which confuses OpenOCD. Currently the user needs to do
> something like set arch riscv:rv32 to work around this.
>
> Is it possible for riscv-tdep.c to have some kind of callback function
> that is called when gdb connects to a server, and for that function to
> change the register width? If so, gdb could read the riscv misa
> (instruction set architecture information) register and transparently
> reconfigure.
>
> I looked, but I didn’t see any obvious callbacks that get called when
> connecting to a target.
>

I don't know much about riscv, so I assume 32-bit variant and 64-bit
variant can _not_ co-exist in one program.  If so, each variant can
be abstracted as a gdbarch.

You need to add two target descriptions for 32-bit and 64-bit variants
respectively, and OpenOCD need to send back the right target
description to GDB.  I assume riscv 32-bit and 64-bit variants have
different registers.

In GDB side, you need two gdbarch instances, 32-bit riscv and 64-bit
riscv.  In riscv_gdbarch_init, look for the feature from the target
description (sent by OpenOCD for example), if 32-bit is found, create
and return gdbarch for 32-bit; if 64-bit is found, create and return
gdbarch for 64-bit.

If 32-bit variant and 64-bit one is quite different, you even can create
two tdep.c files, like riscv32-tdep.c and risc64-tdep.c.

-- 
Yao (齐尧)