From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 63081 invoked by alias); 10 Oct 2016 09:26:36 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 63039 invoked by uid 89); 10 Oct 2016 09:26:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=no version=3.3.2 spammy=connects X-HELO: mail-oi0-f51.google.com Received: from mail-oi0-f51.google.com (HELO mail-oi0-f51.google.com) (209.85.218.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 10 Oct 2016 09:26:25 +0000 Received: by mail-oi0-f51.google.com with SMTP id t73so5930098oie.1 for ; Mon, 10 Oct 2016 02:26:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=FjOW2lDOVek0Erf6KCb7dve/WinGsskXG/3TlgkjUxM=; b=hr6w/gZ9m6dGhcB0T3Y6rLCx/7vVjtUs1gX8KMER7ONPXK4weSlBVwrI1fLRaUvCtM rX4FqRevxxedSvn1/bx03ju8qUXbrips3NofxISXCEG4ytAu0ik3WwLeQKu/FE8HnWmI 0aIq6+rFWfn95vKE7upPnXVuDyek1dpstOLTuNhUyKE3/ufEwdKka18/JISarVuEru2j Pw8dYSfTHlADv8RaYEejXsEbVYW1fMDGdk7NfZp7QDD5mRmKWoHyrtI/gmUy0+T1jNqy a7cw/0QVnz3tc6gOZjW3V7dita8MOrirsiL2MzjKWfk6eulg8764liXEIe9i2QEFJr2p cZog== X-Gm-Message-State: AA6/9RmkhIQSAofYeZrO3Nerk3pjXrGhrxMTquXjUaF5+X4+UUvMKHQzEG2pKCEk/xELH39DybWfNESZiAUEXQ== X-Received: by 10.202.85.78 with SMTP id j75mr24923431oib.0.1476091583493; Mon, 10 Oct 2016 02:26:23 -0700 (PDT) MIME-Version: 1.0 Received: by 10.202.221.3 with HTTP; Mon, 10 Oct 2016 02:26:22 -0700 (PDT) In-Reply-To: References: From: Yao Qi Date: Mon, 10 Oct 2016 09:26:00 -0000 Message-ID: Subject: Re: can target code change architecture setting? To: Tim Newsome Cc: gdb Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-10/txt/msg00015.txt.bz2 On Fri, Oct 7, 2016 at 6:38 PM, Tim Newsome wrote: > I=E2=80=99m working with riscv gdb support. One problem people occasional= ly > run into is that riscv has both 32- and 64-bit variants. The current > gdb code just assumes 64-bit by default (unless a file is specified, > and then it gets the info from the ELF info). If such a gdb connects > to a 32-bit target, bulk register reads end up wonky, and writes send > too much data which confuses OpenOCD. Currently the user needs to do > something like set arch riscv:rv32 to work around this. > > Is it possible for riscv-tdep.c to have some kind of callback function > that is called when gdb connects to a server, and for that function to > change the register width? If so, gdb could read the riscv misa > (instruction set architecture information) register and transparently > reconfigure. > > I looked, but I didn=E2=80=99t see any obvious callbacks that get called = when > connecting to a target. > I don't know much about riscv, so I assume 32-bit variant and 64-bit variant can _not_ co-exist in one program. If so, each variant can be abstracted as a gdbarch. You need to add two target descriptions for 32-bit and 64-bit variants respectively, and OpenOCD need to send back the right target description to GDB. I assume riscv 32-bit and 64-bit variants have different registers. In GDB side, you need two gdbarch instances, 32-bit riscv and 64-bit riscv. In riscv_gdbarch_init, look for the feature from the target description (sent by OpenOCD for example), if 32-bit is found, create and return gdbarch for 32-bit; if 64-bit is found, create and return gdbarch for 64-bit. If 32-bit variant and 64-bit one is quite different, you even can create two tdep.c files, like riscv32-tdep.c and risc64-tdep.c. --=20 Yao (=E9=BD=90=E5=B0=A7)