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* gdbarch_init, ABI, and registers
@ 2017-12-06 20:21 Tim Newsome
  2017-12-07 14:21 ` Handling language trampoline Dmitry Antipov
  2017-12-07 21:22 ` gdbarch_init, ABI, and registers Tim Newsome
  0 siblings, 2 replies; 9+ messages in thread
From: Tim Newsome @ 2017-12-06 20:21 UTC (permalink / raw)
  To: gdb

Still working on RISC-V support…

I’ve taught OpenOCD to provide a target description, so now when connecting
to a target that doesn’t have an FPU, the FPU registers don’t show up.
Obviously I want this reflected in gdb, and I’ve managed to make that work
in some cases. However, it doesn’t always work. Sometimes my target appears
to revert to the case where it just uses the built-in list of registers,
despite being connected to an OpenOCD that I know provides the target
description.

My confusion comes from when riscv_gdbarch_init() is called, and how. With
a bit of instrumenting, I get this output:

+ /opt/riscv/bin/riscv64-unknown-elf-gdb
>>> riscv_gdbarch_init()
>>>     bits_per_word=64
>>>     tdesc_has_register() -> 0
>>>     info.abfd=(nil)
>>>     abi=1073741824
GNU gdb (GDB) 8.0.50.20170724-git
...
(gdb) target extended-remote localhost:38295

target extended-remote localhost:38295
Remote debugging using localhost:38295
>>> riscv_gdbarch_init()
>>>     bits_per_word=64
>>>     tdesc_has_register() -> 1
>>>     info.abfd=(nil)
>>>     abi=1073741824
warning: No executable has been specified and target does not support
determining executable automatically.  Try using the "file" command.
0x00000000800009f0 in ?? ()
(gdb) file HiFive1_debug-32
>>> riscv_gdbarch_init()

>>>     bits_per_word=32
>>>     tdesc_has_register() -> 1
>>>     info.abfd=0x55a8a1f4e7f0
>>>     flavour=5
>>>     abi=0
>>> riscv_gdbarch_init()
>>>     bits_per_word=32
>>>     tdesc_has_register() -> 0
>>>     info.abfd=0x55a8a1f4e7f0
>>>     flavour=5
>>>     abi=0
Reading symbols from HiFive1_debug-32...done.
(gdb) set arch riscv:rv32
>>> riscv_gdbarch_init()
>>>     bits_per_word=32
>>>     tdesc_has_register() -> 1
>>>     info.abfd=0x55a8a1f4e7f0
>>>     flavour=5
>>>     abi=0
The target architecture is assumed to be riscv:rv32

It almost feels like I’m on completely the wrong track by initializing
registers in riscv_gdbarch_init(), but that’s what the ARM and MIPS targets
do. A lot of code in their gdbarch_init() is dedicated to figuring out the
ABI in use. How are ABIs and registers related? In my world view the
hardware has certain registers, and how the software chooses to use those
registers is the ABI. But changing the ABI doesn’t change what registers
exist.

Are there callbacks I can use that are called when we connect to/disconnect
from a remote server like OpenOCD?

Thank you,
Tim
​


^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2017-12-09 11:27 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-06 20:21 gdbarch_init, ABI, and registers Tim Newsome
2017-12-07 14:21 ` Handling language trampoline Dmitry Antipov
2017-12-07 14:58   ` Pedro Alves
2017-12-08  6:39     ` Dmitry Antipov
2017-12-08 11:12       ` Pedro Alves
2017-12-07 21:22 ` gdbarch_init, ABI, and registers Tim Newsome
2017-12-08 12:20   ` Ulrich Weigand
2017-12-08 20:03     ` Tim Newsome
2017-12-09 11:27       ` Ulrich Weigand

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