From: Florian Weimer <fweimer@redhat.com>
To: Dave Martin <Dave.Martin@arm.com>, linux-arm-kernel@lists.infradead.org
Cc: Christoffer Dall <christoffer.dall@linaro.org>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Marc Zyngier <Marc.Zyngier@arm.com>,
Alan Hayward <alan.hayward@arm.com>,
libc-alpha@sourceware.org, gdb@sourceware.org,
Torvald Riegel <triegel@redhat.com>
Subject: Re: [RFC PATCH 00/29] arm64: Scalable Vector Extension core support
Date: Wed, 30 Nov 2016 10:08:00 -0000 [thread overview]
Message-ID: <7a35d1ae-73df-03a5-c9d6-1a52754acf25@redhat.com> (raw)
In-Reply-To: <1480102762-23647-1-git-send-email-Dave.Martin@arm.com>
On 11/25/2016 08:38 PM, Dave Martin wrote:
> The Scalable Vector Extension (SVE) [1] is an extension to AArch64 which
> adds extra SIMD functionality and supports much larger vectors.
>
> This series implements core Linux support for SVE.
>
> Recipents not copied on the whole series can find the rest of the
> patches in the linux-arm-kernel archives [2].
>
>
> The first 5 patches "arm64: signal: ..." factor out the allocation and
> placement of state information in the signal frame. The first three
> are prerequisites for the SVE support patches.
>
> Patches 04-05 implement expansion of the signal frame, and may remain
> controversial due to ABI break issues:
>
> * Discussion is needed on how userspace should detect/negotiate signal
> frame size in order for this expansion mechanism to be workable.
I'm leaning towards a simple increase in the glibc headers (despite the
ABI risk), plus a personality flag to disable really wide vector
registers in case this causes problems with old binaries.
A more elaborate mechanism will likely introduce more bugs than it makes
existing applications working, due to its complexity.
> The remaining patches implement initial SVE support for Linux, with the
> following limitations:
>
> * No KVM/virtualisation support for guests.
>
> * No independent SVE vector length configuration per thread. This is
> planned, but will follow as a separate add-on series.
Per-thread register widths will likely make coroutine switching
(setcontext) and C++ resumable functions/executors quite challenging.
Can you detail your plans in this area?
Thanks,
Florian
next prev parent reply other threads:[~2016-11-30 10:08 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-25 19:39 Dave Martin
2016-11-25 19:41 ` [RFC PATCH 18/29] arm64/sve: signal: Restore FPSIMD/SVE state in rt_sigreturn Dave Martin
2016-11-25 19:41 ` [RFC PATCH 17/29] arm64/sve: signal: Dump Scalable Vector Extension registers to user stack Dave Martin
2016-11-25 19:41 ` [RFC PATCH 16/29] arm64/sve: signal: Add SVE state record to sigcontext Dave Martin
2016-11-25 19:41 ` [RFC PATCH 24/29] arm64/sve: Discard SVE state on system call Dave Martin
2016-11-25 19:42 ` [RFC PATCH 27/29] arm64/sve: ptrace support Dave Martin
2016-11-30 9:56 ` [RFC PATCH 00/29] arm64: Scalable Vector Extension core support Yao Qi
2016-11-30 12:07 ` Dave Martin
2016-11-30 12:22 ` Szabolcs Nagy
2016-11-30 14:10 ` Dave Martin
2016-11-30 12:38 ` Florian Weimer
2016-11-30 13:56 ` Dave Martin
2016-12-01 9:21 ` Florian Weimer
2016-12-01 10:30 ` Dave Martin
2016-12-01 12:19 ` Dave Martin
2016-12-05 10:44 ` Florian Weimer
2016-12-05 11:07 ` Szabolcs Nagy
2016-12-05 15:05 ` Dave Martin
2016-12-02 11:49 ` Dave Martin
2016-12-02 16:34 ` Florian Weimer
2016-12-02 16:59 ` Joseph Myers
2016-12-02 18:21 ` Dave Martin
2016-12-02 21:57 ` Joseph Myers
2016-12-02 21:56 ` Yao Qi
2016-12-05 15:12 ` Dave Martin
2016-12-05 22:42 ` Torvald Riegel
2016-12-06 14:46 ` Dave Martin
2016-11-30 10:08 ` Florian Weimer [this message]
2016-11-30 11:06 ` Szabolcs Nagy
2016-11-30 14:06 ` Dave Martin
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