From: Paul Mundt <lethal@linux-sh.org>
To: Michael Trimarchi <trimarchi@gandalf.sssup.it>
Cc: binom <binomat@gmail.com>, gdb@sourceware.org, linux-sh@vger.kernel.org
Subject: Re: gdbserver on sh4
Date: Tue, 31 Mar 2009 09:07:00 -0000 [thread overview]
Message-ID: <20090331090300.GA1977@linux-sh.org> (raw)
In-Reply-To: <49D1DC2E.2060105@gandalf.sssup.it>
On Tue, Mar 31, 2009 at 11:02:38AM +0200, Michael Trimarchi wrote:
> Paul Mundt wrote:
> >On Tue, Mar 31, 2009 at 10:23:18AM +0200, Michael Trimarchi wrote:
> >>The problem is kernel side and not gdb side. I send a patch to the
> >>linux-sh mailing list. They save the dsp register on the stack before
> >>the processor cpu register but the offset of the struct is wrong
> >>calculated and if the linux kernel is compiled with the dsp option
> >>the PEEKUSR return the wrong register value.
> >>
> >The sanest thing really is just to throw the DSP state in to the thread
> >struct as we do with the FPU, and kill off all of the special DSP state
> >handling we have today. It costs us a thread flag to do lazy context
> >
> I just send a patch that put the dsp state in the thread struct
You sent a patch that cached the enable/disable state in the thread
struct, not the register state. ;-)
> >switching, but it's worth it to get that crap out of the regular register
> >save/restore paths, which is just way too fragile, and has not seen any
> >real maintenance since SH3-DSP.
> >
> So move the save/restore part of the dsp in private data of task and do like
> mips?
Yes.
next prev parent reply other threads:[~2009-03-31 9:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-13 11:23 michael
2009-03-14 7:58 ` michael
2009-03-31 5:46 ` binom
2009-03-31 8:26 ` Michael Trimarchi
2009-03-31 8:56 ` Paul Mundt
2009-03-31 9:05 ` Michael Trimarchi
2009-03-31 9:07 ` Paul Mundt [this message]
2009-03-31 9:11 ` Michael Trimarchi
2009-06-19 15:56 ` damien.courousse.logica
2009-06-19 16:05 ` michael
2009-06-19 16:14 ` damien.courousse.logica
[not found] ` <F81DF98CADE6064F81A746D7C832359367160A@fr-ex009.groupinfra.com>
2009-06-19 16:20 ` michael
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