Re: Resume from Breakpoint - Next Instruction Address or Target Address?

[Daniel Jacobowitz <drow@false.org>]

On Mon, Jan 30, 2006 at 05:48:48PM +0530, Rishi Dixit wrote:
> Hi,
> 
> 
> I am studying about breakpoint functionality in GDB. My study is local
> to the MIPS Simulator. While studying the GDB source, I was referring
> the handling of BREAK instruction. 
> 
> This handling checks for the presence of BREAK instruction in a delay
> slot and alters the Program Counter. However, this information is
> overwritten when the CPU registers are saved before triggering a
> Breakpoint exception. 
> 
> I suspected this would lead to a loss of information regarding the
> target address of jump/branch instruction. To confirm this, I made a
> test case and checked the GDB behavior. 

I don't know - you'd have to ask someone more familiar with the
architecture and the simulator - but I think this is a bug in either
the simulator or GDB; the architecture does provide enough information
to handle this case.  See the documentation of the BD bit in the Cause
register.

> My assumption is that since the breakpoint is hit after the jump/branch
> instruction has been executed, the resume should be from the target
> address. 

No, generally we want to resume where we were, not where we're going
to.  The resume should be back on the jump.  I have no idea if GDB
implements that.

-- 
Daniel Jacobowitz
CodeSourcery