* Troubles building cris target @ 2005-03-15 21:51 Jim Blandy 2005-03-15 23:09 ` Hans-Peter Nilsson 0 siblings, 1 reply; 5+ messages in thread From: Jim Blandy @ 2005-03-15 21:51 UTC (permalink / raw) To: hans-peter.nilsson, orjan.friberg; +Cc: gdb When I try to build the GDB/sim sources from sources.redhat.com CVS on an AMD64 Fedora Core 2 system, the build dies trying to link the sim/cris/run executable with the errors below. This looks simple to fix, but I haven't followed it through. If you folks have some time to look at it, that'd be great. Or, if you don't think you'll be able to get to it, could we mark cris as 'broken' in gdb/MAINTAINERS in the meantime, so gdb_mbuild.sh will go through? gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"crisv32"' -DPROFILE=1 -DWITH_PROFILE=-1 -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_ENVIRONMENT=ALL_ENVIRONMENT -DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN -DWITH_SCACHE=16384 -I. -I/home/jimb/gdb/src/sim/cris -I../common -I/home/jimb/gdb/src/sim/cris/../common -I../../include -I/home/jimb/gdb/src/sim/cris/../../include -I../../bfd -I/home/jimb/gdb/src/sim/cris/../../bfd -I../../opcodes -I/home/jimb/gdb/src/sim/cris/../../opcodes -I../../intl -I/home/jimb/gdb/src/sim/cris/../../intl -g3 -o run \ nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a -lnsl libsim.a(mloopv10f.o)(.text+0x3c2b): In function `crisv10f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1285: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x3ff2):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1348: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x43fc):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1411: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x479d):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1470: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x4b45):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1529: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x4fcc):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1607: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x5464):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1686: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x5903):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1765: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x5c65):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1825: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x5fc2):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1884: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x6328):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1943: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x667e):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:2002: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x6b07):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:2080: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x6f99):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:2159: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x72fa):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:2219: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x7651):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:2278: more undefined references to `SUBCSI' follow libsim.a(mloopv10f.o)(.text+0x12f88): In function `crisv10f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5575: undefined reference to `ADDCQI' libsim.a(mloopv10f.o)(.text+0x133be):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5642: undefined reference to `ADDCHI' libsim.a(mloopv10f.o)(.text+0x137fe):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5709: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x13cf6):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5791: undefined reference to `ADDCQI' libsim.a(mloopv10f.o)(.text+0x14327):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5878: undefined reference to `ADDCHI' libsim.a(mloopv10f.o)(.text+0x14963):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:5965: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x14dce):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6029: undefined reference to `ADDCQI' libsim.a(mloopv10f.o)(.text+0x151c0):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6096: undefined reference to `ADDCHI' libsim.a(mloopv10f.o)(.text+0x155bd):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6163: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x15cf4):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6289: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x160ff):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6352: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x165f9):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6434: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x16b93):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6517: undefined reference to `ADDCSI' libsim.a(mloopv10f.o)(.text+0x16ffd):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:6581: more undefined references to `ADDCSI' follow libsim.a(mloopv10f.o)(.text+0x1961a): In function `crisv10f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7191: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x19a50):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7258: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x19e90):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7325: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1a388):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7407: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x1a9b8):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7494: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x1aff4):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7581: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1b45f):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7645: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x1b851):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7712: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x1bc4e):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7779: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1c059):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7842: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1c464):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7905: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1c95e):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:7987: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1cef9):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8070: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x1d363):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8134: more undefined references to `SUBCSI' follow libsim.a(mloopv10f.o)(.text+0x1fb77): In function `crisv10f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8777: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x1ff63):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8844: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x2035d):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8911: undefined reference to `SUBCSI' libsim.a(mloopv10f.o)(.text+0x20814):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:8996: undefined reference to `SUBCQI' libsim.a(mloopv10f.o)(.text+0x20c69):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:9079: undefined reference to `SUBCHI' libsim.a(mloopv10f.o)(.text+0x210c8):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:9162: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x31df): In function `crisv32f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1215: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x3541):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1278: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x38bc):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1341: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x3c3a):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1400: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x3fc6):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1459: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x43c5):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1537: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x47f0):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1616: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x4c20):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1695: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x4f8d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1755: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x52e7):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1814: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x5677):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1873: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x59ca):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:1932: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x5dcf):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:2010: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x61e0):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:2089: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x6541):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:2149: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x6895):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:2208: more undefined references to `SUBCSI' follow libsim.a(mloopv32f.o)(.text+0x1836d): In function `crisv32f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:5681: undefined reference to `ADDCQI' libsim.a(mloopv32f.o)(.text+0x18751):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:5748: undefined reference to `ADDCHI' libsim.a(mloopv32f.o)(.text+0x18b6d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:5815: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x18fc6):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:5897: undefined reference to `ADDCQI' libsim.a(mloopv32f.o)(.text+0x19451):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:5984: undefined reference to `ADDCHI' libsim.a(mloopv32f.o)(.text+0x19914):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6071: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x19cd8):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6135: undefined reference to `ADDCQI' libsim.a(mloopv32f.o)(.text+0x1a0ad):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6202: undefined reference to `ADDCHI' libsim.a(mloopv32f.o)(.text+0x1a4ba):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6269: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x1a871):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6332: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x1ac28):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6395: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x1b081):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6477: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x1b4e6):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6560: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x1b89b):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:6624: more undefined references to `ADDCSI' follow libsim.a(mloopv32f.o)(.text+0x1d794): In function `crisv32f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7168: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x1db78):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7235: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x1df94):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7302: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x1e3ed):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7384: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x1e878):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7471: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x1ed3b):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7558: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x1f0ff):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7622: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x1f4d4):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7689: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x1f8e1):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7756: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x1fc98):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7819: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x2004f):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7882: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x204a8):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:7964: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x2090d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:8047: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x20cc2):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:8111: more undefined references to `SUBCSI' follow libsim.a(mloopv32f.o)(.text+0x22bbc): In function `crisv32f_engine_run_full': /home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:8657: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x2301d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:8742: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x233e2):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:8809: undefined reference to `ADDCSI' libsim.a(mloopv32f.o)(.text+0x23e0f):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9038: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x241de):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9105: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x245e8):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9172: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x24a44):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9257: undefined reference to `SUBCQI' libsim.a(mloopv32f.o)(.text+0x24e3d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9340: undefined reference to `SUBCHI' libsim.a(mloopv32f.o)(.text+0x25261):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:9423: undefined reference to `SUBCSI' libsim.a(mloopv32f.o)(.text+0x2791d):/home/jimb/gdb/src/sim/cris/semcrisv32f-switch.c:10129: undefined reference to `ADDCSI' collect2: ld returned 1 exit status make[2]: *** [run] Error 1 make[2]: Leaving directory `/home/jimb/gdb/mbuild/cris-elf/sim/cris' make[1]: *** [all] Error 1 make[1]: Leaving directory `/home/jimb/gdb/mbuild/cris-elf/sim' make: *** [all-sim] Error 2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Troubles building cris target 2005-03-15 21:51 Troubles building cris target Jim Blandy @ 2005-03-15 23:09 ` Hans-Peter Nilsson 2005-03-16 17:57 ` Jim Blandy 0 siblings, 1 reply; 5+ messages in thread From: Hans-Peter Nilsson @ 2005-03-15 23:09 UTC (permalink / raw) To: jimb; +Cc: cgen, orjan.friberg, gdb > From: Jim Blandy <jimb@redhat.com> > Date: 15 Mar 2005 16:48:01 -0500 > When I try to build the GDB/sim sources from sources.redhat.com CVS on > an AMD64 Fedora Core 2 system, the build dies trying to link the > sim/cris/run executable with the errors below. JFTR, I built sim successfully on i686-pc-linux-gnu (FC2) with CVS as of "Tue Mar 15 15:09:24 UTC 2005". > This looks simple to fix, but I haven't followed it through. CGEN bugs are simple? Let's talk. > gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"crisv32"' -DPROFILE=1 -DWITH_PROFILE=-1 -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_ENVIRONMENT=ALL_ENVIRONMENT -DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN -DWITH_SCACHE=16384 -I. -I/home/jimb/gdb/src/sim/cris -I../common -I/home/jimb/gdb/src/sim/cris/../common -I../../include -I/home/jimb/gdb/src/sim/cris/../../include -I../../bfd -I/home/jimb/gdb/src/sim/cris/../../bfd -I../../opcodes -I/home/jimb/gdb/src/sim/cris/../../opcodes -I../../intl -I/home/jimb/gdb/src/sim/cris/../../intl -g3 -o run \ > nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a -lnsl > libsim.a(mloopv10f.o)(.text+0x3c2b): In function `crisv10f_engine_run_full': > /home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1285: undefined reference to `ADDCSI' > libsim.a(mloopv10f.o)(.text+0x3ff2):/home/jimb/gdb/src/sim/cris/semcrisv10f-switch.c:1348: undefined reference to `SUBCSI' Can you please test this patch? 2005-03-16 Hans-Peter Nilsson <hp@axis.com> * cris/sim-main.h: Don't include cgen-ops.h. Define ANDIF specifically. --- sim-main.h Fri Jan 28 05:29:00 2005 +++ /tmp/sim-main.h Wed Mar 16 00:00:56 2005 @@ -57,8 +57,11 @@ do { \ #include "cgen-sim.h" #include "cris-sim.h" -/* For occurrences of ANDIF in decodev32.c. */ -#include "cgen-ops.h" +/* For occurrences of ANDIF in decodev32.c. We can't '#include + "cgen-ops.h"' here, as that'll break the outlining of operators in + sim/common/cgen-utils.c. FIXME: CGEN bug; there should be no ANDIF:s + in decodev32.c. */ +#define ANDIF(x, y) ((x) && (y)) \f struct cris_sim_mmapped_page { USI addr; brgds, H-P ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Troubles building cris target 2005-03-15 23:09 ` Hans-Peter Nilsson @ 2005-03-16 17:57 ` Jim Blandy 2005-03-16 18:24 ` Hans-Peter Nilsson 0 siblings, 1 reply; 5+ messages in thread From: Jim Blandy @ 2005-03-16 17:57 UTC (permalink / raw) To: Hans-Peter Nilsson; +Cc: cgen, orjan.friberg, gdb Hans-Peter Nilsson <hans-peter.nilsson@axis.com> writes: > JFTR, I built sim successfully on i686-pc-linux-gnu (FC2) with > CVS as of "Tue Mar 15 15:09:24 UTC 2005". Hm. Our systems look identical except for the processor. Do you know why it builds for you, but not for me? > Can you please test this patch? > > 2005-03-16 Hans-Peter Nilsson <hp@axis.com> > > * cris/sim-main.h: Don't include cgen-ops.h. Define ANDIF specifically. It dies differently now: gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"crisv32"' -DPROFILE=1 -DWITH_PROFILE=-1 -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_ENVIRONMENT=ALL_ENVIRONMENT -DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN -DWITH_SCACHE=16384 -I. -I/home/jimb/gdb/src/sim/cris -I../common -I/home/jimb/gdb/src/sim/cris/../common -I../../include -I/home/jimb/gdb/src/sim/cris/../../include -I../../bfd -I/home/jimb/gdb/src/sim/cris/../../bfd -I../../opcodes -I/home/jimb/gdb/src/sim/cris/../../opcodes -I../../intl -I/home/jimb/gdb/src/sim/cris/../../intl -g3 -o run \ nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a -lnsl libsim.a(decodev10.o)(.text+0x771a): In function `crisv10f_decode': /home/jimb/gdb/src/sim/cris/decodev10.c:5059: undefined reference to `EXTHISI' libsim.a(decodev10.o)(.text+0x77fb):/home/jimb/gdb/src/sim/cris/decodev10.c:5087: undefined reference to `EXTHISI' libsim.a(decodev32.o)(.text+0x7219): In function `crisv32f_decode': /home/jimb/gdb/src/sim/cris/decodev32.c:4587: undefined reference to `EXTHISI' libsim.a(decodev32.o)(.text+0x72f7):/home/jimb/gdb/src/sim/cris/decodev32.c:4615: undefined reference to `EXTHISI' collect2: ld returned 1 exit status make[2]: *** [run] Error 1 make[2]: Leaving directory `/home/jimb/gdb/mbuild/cris-elf/sim/cris' make[1]: *** [all] Error 1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Troubles building cris target 2005-03-16 17:57 ` Jim Blandy @ 2005-03-16 18:24 ` Hans-Peter Nilsson 2005-03-24 6:20 ` Hans-Peter Nilsson 0 siblings, 1 reply; 5+ messages in thread From: Hans-Peter Nilsson @ 2005-03-16 18:24 UTC (permalink / raw) To: jimb; +Cc: hans-peter.nilsson, cgen, orjan.friberg, gdb > From: Jim Blandy <jimb@redhat.com> > Date: 16 Mar 2005 12:53:10 -0500 > Hans-Peter Nilsson <hans-peter.nilsson@axis.com> writes: > > JFTR, I built sim successfully on i686-pc-linux-gnu (FC2) with > > CVS as of "Tue Mar 15 15:09:24 UTC 2005". > > Hm. Our systems look identical except for the processor. Do you know > why it builds for you, but not for me? I can only assume that inlining limits are different. (Either we're using different GCC versions or inlining parameters for x86_64 trig differently.) The comment in the patch mentioned outlining of operator functions. Without the patch, they are never outlined, so if there's a call to the outlined function (as happened for you), it will not be found. > It dies differently now: > > gcc -DHAVE_CONFIG_H -DWITH_DEFAULT_MODEL='"crisv32"' -DPROFILE=1 -DWITH_PROFILE=-1 -DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT -DWITH_ENVIRONMENT=ALL_ENVIRONMENT -DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN -DWITH_SCACHE=16384 -I. -I/home/jimb/gdb/src/sim/cris -I../common -I/home/jimb/gdb/src/sim/cris/../common -I../../include -I/home/jimb/gdb/src/sim/cris/../../include -I../../bfd -I/home/jimb/gdb/src/sim/cris/../../bfd -I../../opcodes -I/home/jimb/gdb/src/sim/cris/../../opcodes -I../../intl -I/home/jimb/gdb/src/sim/cris/../../intl -g3 -o run \ > nrun.o libsim.a ../../bfd/libbfd.a ../../opcodes/libopcodes.a ../../libiberty/libiberty.a -lnsl > libsim.a(decodev10.o)(.text+0x771a): In function `crisv10f_decode': > /home/jimb/gdb/src/sim/cris/decodev10.c:5059: undefined reference to `EXTHISI' Ugh. Looks like I'd need to #define EXTHISI too, perhaps others. But the obvious just dawned on me: the generated decode*.c should have an '#include "cgen-ops.h"'. Completely untested. CGENers, please comment. Decoding of instruction fields should be able to use the usual operators. Dunno if that's supposed to be handled elsewhere. Maybe this is related to the problem generating SID CPU files since about a year (reported before, no clue received). Ok to commit if it works? 2005-03-16 Hans-Peter Nilsson <hp@axis.com> * sim-decode.scm (cgen-decode.c): Include cgen-ops.h. Index: sim-decode.scm =================================================================== RCS file: /cvs/src/src/cgen/sim-decode.scm,v retrieving revision 1.9 diff -c -p -r1.9 sim-decode.scm *** sim-decode.scm 8 Jul 2003 16:19:35 -0000 1.9 --- sim-decode.scm 16 Mar 2005 18:17:07 -0000 *************** const IDESC * *** 582,587 **** --- 582,588 ---- #define WANT_CPU_@CPU@ #include \"sim-main.h\" + #include \"cgen-ops.h\" #include \"sim-assert.h\"\n\n" (lambda () (-gen-decode-insn-globals (non-multi-insns (non-alias-insns (current-insn-list))))) brgds, H-P ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: Troubles building cris target 2005-03-16 18:24 ` Hans-Peter Nilsson @ 2005-03-24 6:20 ` Hans-Peter Nilsson 0 siblings, 0 replies; 5+ messages in thread From: Hans-Peter Nilsson @ 2005-03-24 6:20 UTC (permalink / raw) To: cgen, gdb; +Cc: jimb > Date: Wed, 16 Mar 2005 19:24:21 +0100 > From: Hans-Peter Nilsson <hp@axis.com> > Ok to commit if it works? > > 2005-03-16 Hans-Peter Nilsson <hp@axis.com> > > * sim-decode.scm (cgen-decode.c): Include cgen-ops.h. That patch worked, as in compiles and cgen-utils.o contains the intended symbols for cris-sim. Calling again: any CGEN maintainer care to comment, perhaps approve? See earlier post for the obvious patch. For CRIS, removing the sim-main.h kludge as per below is necessary too. And of course, rebuilding decodev{10,32}.c is also necessary. Though until I get approval or other feedback from CGEN, I've instead committed the following horrible patch, which fixes up the generated decodev{10,32}.c after the fact but as soon as it's generated. (I couldn't find any system where gcc outlined some operator calls like what happens for Jim Blandy, but then again I don't have access to an amd64 system with FC2. SuSE's gcc-3.3.3 on amd64 does inline. Ditto gcc-3.2 and 3.4 for various hewlett-packard-testdrive systems.) Jim, please update and retry. I committed regen of all files; most changes in (other) regened files were the copyright blurb, but there seems to have been some gcc-4.0 fixes by Alan Modra. Can't be all bad. :-) Committed, after running the test-suite (which I haven't contributed yet, doh!) except the C tests. * cris/Makefile.in (stamp-v10fcpu, stamp-v32fcpu): Add kludge to include cgen-ops.h in decodev10.c and decodev32.c. * cris/sim-main.h: Don't include cgen-ops.h here. * cris/arch.c, cris/arch.h, cris/cpuall.h, cris/cpuv10.c, cris/cpuv10.h, cris/cpuv32.c, cris/cpuv32.h, cris/cris-desc.c, cris/cris-desc.h, cris/cris-opc.h, cris/decodev10.c, cris/decodev10.h, cris/decodev32.c, cris/decodev32.h, cris/modelv10.c, cris/modelv32.c, cris/semcrisv10f-switch.c, cris/semcrisv32f-switch.c: Regenerate. Index: sim-main.h =================================================================== RCS file: /cvs/src/src/sim/cris/sim-main.h,v retrieving revision 1.1 diff -p -c -u -p -r1.1 sim-main.h --- sim-main.h 28 Jan 2005 04:29:00 -0000 1.1 +++ sim-main.h 24 Mar 2005 06:06:03 -0000 @@ -56,9 +56,6 @@ do { \ #include "sim-base.h" #include "cgen-sim.h" #include "cris-sim.h" - -/* For occurrences of ANDIF in decodev32.c. */ -#include "cgen-ops.h" \f struct cris_sim_mmapped_page { USI addr; Index: Makefile.in =================================================================== RCS file: /cvs/src/src/sim/cris/Makefile.in,v retrieving revision 1.1 diff -p -c -u -p -r1.1 Makefile.in --- Makefile.in 28 Jan 2005 04:28:59 -0000 1.1 +++ Makefile.in 24 Mar 2005 06:06:03 -0000 @@ -140,11 +140,14 @@ stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH touch stamp-arch arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch +# The sed-hack is supposed to be temporary, until we get CGEN to emit it. stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ archfile=$(CGEN_CPU_DIR)/cris.cpu \ cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)" $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c + sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev10.c > decodev10.c.tmp + mv decodev10.c.tmp $(srcdir)/decodev10.c touch stamp-v10fcpu cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu @@ -153,6 +156,8 @@ stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_C archfile=$(CGEN_CPU_DIR)/cris.cpu \ cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)" $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c + sed -ne 'p; s/^\(#include "sim-assert.h"\)$$/#include "cgen-ops.h"/p' < $(srcdir)/decodev32.c > decodev32.c.tmp + mv decodev32.c.tmp $(srcdir)/decodev32.c touch stamp-v32fcpu cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu brgds, H-P ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2005-03-24 6:20 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2005-03-15 21:51 Troubles building cris target Jim Blandy 2005-03-15 23:09 ` Hans-Peter Nilsson 2005-03-16 17:57 ` Jim Blandy 2005-03-16 18:24 ` Hans-Peter Nilsson 2005-03-24 6:20 ` Hans-Peter Nilsson
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