Re: multi-arch and CALL_DUMMY_BREAKPOINT_OFFSET

[Richard Earnshaw <rearnsha@arm.com>]

> > I guess I'm going to find several things like this...
> 
> 
> > Well it appears that in a multi-arch gdb (even at level 1), 
> > CALL_DUMMY_BREAKPOINT_OFFSET can only be a constant for any particular 
> > architecture.  This is a problem, because on the ARM it is currently a 
> > function that returns one of two values depending on whether the 
> > call-dummy stub has to be ARM code or Thumb code.  Note that both types of 
> > code can exist within a single application and it is not always safe to 
> > assume that every function is interworking safe.
> 
> 
> Oops :-(  People keep finding things I thought would be constant but are 
> not.

Indeed, it appears the arm isn't the only machine like this, though...
> > 
> > Any suggestions?  Can I diddle with the gdbarch setting dynamically -- eg 
> > by calling gdbarch_set_call_dummy_breakpoint_offset() from within 
> > arm_fix_call_dummy()?  It's quite gross, but it might work.
> 

And this is what sparc-tdep.c seems to do...  In that case it's because 
the breakpoint position will change if the result is in a structure, or 
something like that.


> 
> > Long term it would probably be better to rewrite the call-dummy handling 
> > to remove the covert variable that is used to communicate between the 
> > various call-dummy stubs, but I'd rather not do that now.
> 
> 
>    /* CALL_DUMMY is an array of words (REGISTER_SIZE), but each word
>       is in host byte order.  Before calling FIX_CALL_DUMMY, we byteswap it
>       and remove any extra bytes which might exist because ULONGEST is
>       bigger than REGISTER_SIZE.
> 
>       NOTE: This is pretty wierd, as the call dummy is actually a
>       sequence of instructions.  But CISC machines will have
>       to pack the instructions into REGISTER_SIZE units (and
>       so will RISC machines for which INSTRUCTION_SIZE is not
>       REGISTER_SIZE).
> 
>       NOTE: This is pretty stupid.  CALL_DUMMY should be in strict
>       target byte order. */
> 
> You would not be alone.

I was thinking of the ARM part of the call-dummy code, not the whole 
thing, but yes, that needs re-writing too :^)

R.