MIPS CPU register order

MIPS CPU register order

[Sumit Garg]

Hi All,
I am working on enhancing the GDB, to process our properietory core files.
Currently I am dumping the registers in the .reg segment in the following
order.
    sr, pc, lo, hi, gpreg[32], cause, fpcsr.

However, I am not sure if this is the order in which the function
read_registers(), would expect the registers to be. Can somebody pls give me
pointers to where the GDB register order for mips processors is stored.

Thanks
Sumit

Re: MIPS CPU register order

[Daniel Jacobowitz]

On Fri, Jun 22, 2001 at 10:54:24AM -0700, Sumit Garg wrote:
> Hi All,
> I am working on enhancing the GDB, to process our properietory core files.
> Currently I am dumping the registers in the .reg segment in the following
> order.
>     sr, pc, lo, hi, gpreg[32], cause, fpcsr.
> 
> However, I am not sure if this is the order in which the function
> read_registers(), would expect the registers to be. Can somebody pls give me
> pointers to where the GDB register order for mips processors is stored.

[warning: non multi-arch aware answer]

The order in the core file can be whatever you want.  In your target
nat file, you'll have functions supply_gregset and supply_fpregset,
which transform the registers into the form GDB expects.  Usually,
you'll want to make the order in the core file match gregset_t and
fpregset_t, since that's what core-regset.c expects.

-- 
Daniel Jacobowitz                           Carnegie Mellon University
MontaVista Software                         Debian GNU/Linux Developer