Re: Unreviewed patch: add include/gdb/sim-sh.h (Was: Re: SH simulator register numbers: include/gdb/sim-sh.h)

[Elena Zannoni <ezannoni@redhat.com>]

Sorry.
Can you format the file with one register per line?
Take a look at sim-d10v.h, now that Andrew cleaned it up.

I am not sure that leaving holes in the register numbers is a good idea.

Does this work with gdb as it is now?

Elena


Joern Rennecke writes:
 > Joern Rennecke wrote:
 > > 
 > > > BTW, GDB has started moving the include/sim-*.h files into
 > > > include/gdb/sim-*.h, but otherwise, yes.
 > > 
 > > Right, so the simulator interface would go into include/gdb/sim-sh.h .
 > > 
 > > Fri May 10 14:58:33 2002  J"orn Rennecke <joern.rennecke@superh.com>
 > > 
 > >         * sim-sh.h: New file, from include/sim-sh64.h.  Added
 > >         SH1-SH4 / SH-DSP register numbers, moved SH5 register numbers,
 > >         added full set of control registers.
 > > 
 > > --
 > > --------------------------
 > > SuperH
 > > 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
 > > T:+44 1454 462330
 > > 
 > >   --------------------------------------------------------------------------------
 > > /* This file defines the interface between the sh64 simulator and gdb.
 > >    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 > > 
 > > This file is part of GDB.
 > > 
 > > This program is free software; you can redistribute it and/or modify
 > > it under the terms of the GNU General Public License as published by
 > > the Free Software Foundation; either version 2 of the License, or
 > > (at your option) any later version.
 > > 
 > > This program is distributed in the hope that it will be useful,
 > > but WITHOUT ANY WARRANTY; without even the implied warranty of
 > > MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 > > GNU General Public License for more details.
 > > 
 > > You should have received a copy of the GNU General Public License
 > > along with this program; if not, write to the Free Software
 > > Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 > > 
 > > #if !defined (SIM_SH_H)
 > > #define SIM_SH_H
 > > 
 > > #ifdef __cplusplus
 > > extern "C" { // }
 > > #endif
 > > 
 > > /* The simulator makes use of the following register information. */
 > > 
 > > enum
 > >   {
 > >     SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM,
 > >     SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM,
 > >     SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM,
 > >     SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM,
 > >     SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM,
 > >     SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM,
 > >     SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM,
 > >     SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM,
 > >     SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */
 > >     /* sh[3]-dsp */
 > >     SIM_SH_DSR_REGNUM = 24,
 > >     SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM,
 > >     SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM,
 > >     SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM,
 > >     SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM,
 > >     SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM,
 > >     SIM_SH_MOD_REGNUM = 40,
 > >     SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
 > >     SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */
 > >     SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */
 > >     SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */
 > >     SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */
 > >     SIM_SH_XF0_REGNUM = 59,
 > >     SIM_SH_SGR_REGNUM = 75,
 > >     SIM_SH_DBR_REGNUM = 76,
 > >     SIM_SH4_NUM_REGS,
 > >     /* 77..127: room for expansion.  */
 > > 
 > > 
 > >     SIM_SH64_R0_REGNUM = 128,
 > >     SIM_SH64_SP_REGNUM   = SIM_SH64_R0_REGNUM+15,
 > >     SIM_SH64_PC_REGNUM   = SIM_SH64_R0_REGNUM+64,
 > >     /* 64 64-bit control registers */
 > >     SIM_SH64_CR0_REGNUM  = SIM_SH64_R0_REGNUM+65,
 > >     SIM_SH64_SR_REGNUM   = SIM_SH64_CR0_REGNUM,    /* Status reg            */
 > >     SIM_SH64_SSR_REGNUM  = SIM_SH64_CR0_REGNUM+1,  /* Saved status reg      */
 > >     SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2,  /* Panic-saved status reg*/
 > >     SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4,  /* Interrupt event reg   */
 > >     SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5,  /* Exception event reg   */
 > >     SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception
 > >                                                                   event reg */
 > >     SIM_SH64_TRA_REGNUM  = SIM_SH64_CR0_REGNUM+7,  /* TRAP exception reg    */
 > >     SIM_SH64_SPC_REGNUM  = SIM_SH64_CR0_REGNUM+8,  /* Saved program counter */
 > >     SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9,  /* Panic-saved program
 > >                                                                     counter */
 > >     SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector          */
 > >     SIM_SH64_VBR_REGNUM  = SIM_SH64_CR0_REGNUM+11, /* Vector base register  */
 > >     SIM_SH64_TEA_REGNUM  = SIM_SH64_CR0_REGNUM+13, /* Faulting effective
 > >                                                            address register */
 > >     SIM_SH64_DCR_REGNUM  = SIM_SH64_CR0_REGNUM+16, /* Debug control reg     */
 > >     SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0     */
 > >     SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1     */
 > >     SIM_SH64_CTC_REGNUM  = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter    */
 > >     SIM_SH64_USR_REGNUM  = SIM_SH64_CR0_REGNUM+63, /* User-accessible
 > >                                                             status register */
 > >     SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128,
 > >     SIM_SH64_TR0_REGNUM  = SIM_SH64_R0_REGNUM+129,
 > >     SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137,
 > >     SIM_SH64_FR0_REGNUM  = SIM_SH64_R0_REGNUM+138
 > >   };
 > > 
 > > enum
 > >   {
 > >     SIM_SH64_NUM_REGS = 202,  /* total number of architectural registers */
 > >     SIM_SH64_NR_R_REGS = 64, /* number of general registers */
 > >     SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
 > >     SIM_SH64_NR_FP_REGS = 64, /* number of floating point registers */
 > > 
 > >     SIM_SH64_FPSCR_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8,
 > >     SIM_SH64_FR0_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8 + 4
 > >   };
 > > 
 > > enum
 > >   {
 > >     SIM_SH4_REG_BYTES = SIM_SH4_NUM_REGS * 4,
 > >     SIM_SH64_REG_BYTES = SIM_SH64_NUM_REGS * 8 - (SIM_SH64_NR_FP_REGS + 1) * 4
 > >   };
 > > 
 > > #ifdef __cplusplus
 > > }
 > > #endif
 > > 
 > > #endif
 > 
 > -- 
 > --------------------------
 > SuperH
 > 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ
 > T:+44 1454 462330