From: Balazs Scheidler <bazsi@balabit.hu>
To: Daniel Jacobowitz <drow@false.org>
Cc: Jim Blandy <jimb@codesourcery.com>,
"Mohammed, Moqtadir" <Moqtadir_Mohammed@reyrey.com>,
gdb@sourceware.org
Subject: Re: Can this be happening?
Date: Thu, 05 Jul 2007 19:26:00 -0000 [thread overview]
Message-ID: <1183663584.10465.23.camel@bzorp.balabit> (raw)
In-Reply-To: <20070703215751.GA941@caradoc.them.org>
On Tue, 2007-07-03 at 17:57 -0400, Daniel Jacobowitz wrote:
> On Tue, Jul 03, 2007 at 02:38:51PM -0700, Jim Blandy wrote:
> > I don't know why the upper bits would be set. GDB may be
> > misinterpreting the information in the core file.
>
> The kernel dumps it as 32-bit too. It's not clear what those bits are
> for, but I bet they're really in your core dump and you should ask the
> kernel developers.
>
> Moves from the segment registers may leave implementation defined data
> in the upper half register - but that's only for fairly old Intel
> processors.
>
IIRC the processor-defined TSS (Task State Segment) uses 32 bit values
for segment registers, although as I know TSS is not used anymore by
recent kernels.
--
Bazsi
next prev parent reply other threads:[~2007-07-05 19:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-29 23:03 Mohammed, Moqtadir
2007-07-03 21:38 ` Jim Blandy
2007-07-03 21:54 ` Mark Kettenis
2007-07-03 21:58 ` Daniel Jacobowitz
2007-07-05 19:26 ` Balazs Scheidler [this message]
2007-07-03 22:16 Mohammed, Moqtadir
2007-07-03 22:46 Mohammed, Moqtadir
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