From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24861 invoked by alias); 5 Jul 2007 19:26:37 -0000 Received: (qmail 24853 invoked by uid 22791); 5 Jul 2007 19:26:36 -0000 X-Spam-Check-By: sourceware.org Received: from www.balabit.hu (HELO lists.balabit.hu) (212.92.18.33) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 05 Jul 2007 19:26:30 +0000 Received: from balabit.hu (unknown [10.80.0.254]) by lists.balabit.hu (Postfix) with ESMTP id 76FFFB5594 for ; Thu, 5 Jul 2007 21:26:24 +0200 (CEST) Subject: Re: Can this be happening? From: Balazs Scheidler To: Daniel Jacobowitz Cc: Jim Blandy , "Mohammed, Moqtadir" , gdb@sourceware.org In-Reply-To: <20070703215751.GA941@caradoc.them.org> References: <20070703215751.GA941@caradoc.them.org> Content-Type: text/plain Date: Thu, 05 Jul 2007 19:26:00 -0000 Message-Id: <1183663584.10465.23.camel@bzorp.balabit> Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2007-07/txt/msg00043.txt.bz2 On Tue, 2007-07-03 at 17:57 -0400, Daniel Jacobowitz wrote: > On Tue, Jul 03, 2007 at 02:38:51PM -0700, Jim Blandy wrote: > > I don't know why the upper bits would be set. GDB may be > > misinterpreting the information in the core file. > > The kernel dumps it as 32-bit too. It's not clear what those bits are > for, but I bet they're really in your core dump and you should ask the > kernel developers. > > Moves from the segment registers may leave implementation defined data > in the upper half register - but that's only for fairly old Intel > processors. > IIRC the processor-defined TSS (Task State Segment) uses 32 bit values for segment registers, although as I know TSS is not used anymore by recent kernels. -- Bazsi