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From: "Daniel Berlin" <dberlin@msn.com>
To: <jtc@redback.com>, <gdb@cygnus.com>
Cc: "Jeff Epler" <jepler@inetnebr.com>, "Jim Blandy" <jimb@cygnus.com>
Subject: Re: MMX registers on x86?
Date: Wed, 14 Apr 1999 16:43:00 -0000	[thread overview]
Message-ID: <001d01be8799$59947480$8d8f9780@DANIELBE> (raw)
In-Reply-To: <5m7lrevrc4.fsf@jtc.redbacknetworks.com>

However, it might be better to just add some mechanism to define "special"
registers (Fer instance, ,3dnow/KNI/MMX) that are in some way different from
the rest of the processor registers, be it in size/usage/whatever.
I'm about to add KNI support to the BeOS port, as well as MMX and 3DNow
support, and i'd rather have some standard supported way of doing it than
making another hack that someone will have to futz with and learn the
reasoning behind a year or two down the line.  Or when something like
Altivec comes along, it wouldn't take major retrofitting and port hacking
(every single target that can run on that processor with a different -nat
file) to do.
--Dan
>
> This is an all-to-easy comment to make now, but I believe what should
> have happened is that the tm-i386.h file should have defined the FPU
> registers as they are in the processor; and those targets that can't
> support the FPU should have been forced to make whatever provisions
> necessary to adjust.  It's a bit difficult to make that change now,
> since it's hard to tell what targets are going to break because of
> the chage.
>
> --jtc
>
> --
> J.T. Conklin
> RedBack Networks



  parent reply	other threads:[~1999-04-14 16:43 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
1999-04-01  0:00 Jeff Epler
1999-04-12 11:41 ` Jim Blandy
1999-04-12 13:12   ` Jeff Epler
1999-04-14 14:14   ` J.T. Conklin
1999-04-14 15:18     ` J.T. Conklin
1999-04-14 16:43     ` Daniel Berlin [this message]
1999-04-14 17:59       ` Stan Shebs
1999-04-14 18:55         ` Stan Shebs

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