RFA: sim: fix concatenation of E500 high / low gpr halves

[Jim Blandy <jimb@redhat.com>]

This fixes various failures in e500-regs.exp, in which the value
assigned to evfoo.v2_int32[0] is always read back as 0xffffffff when
evfoo.v2_int32[1] has its top bit set.

2004-06-14  Jim Blandy  <jimb@redhat.com>

	* e500_registers.h (EVR): Cast the 32-bit value of the GPR to an
	unsigned type before or-ing it with a 64-bit value.

Index: sim/ppc/e500_registers.h
===================================================================
RCS file: /cvs/src/src/sim/ppc/e500_registers.h,v
retrieving revision 1.1
diff -c -p -r1.1 e500_registers.h
*** sim/ppc/e500_registers.h	22 Jun 2003 16:48:12 -0000	1.1
--- sim/ppc/e500_registers.h	14 Jun 2004 20:03:06 -0000
*************** struct e500_regs {
*** 79,83 ****
  /* e500 register high bits */
  #define GPRH(N)		cpu_registers(processor)->e500.gprh[N]
  
! /* e500 unified vector register */
! #define EVR(N)		((((unsigned64)GPRH(N)) << 32) | GPR(N))
--- 79,86 ----
  /* e500 register high bits */
  #define GPRH(N)		cpu_registers(processor)->e500.gprh[N]
  
! /* e500 unified vector register
!    We need to cast the gpr value to an unsigned type so that it
!    doesn't get sign-extended when it's or-ed with a 64-bit value; that
!    would wipe out the upper 32 bits of the register's value.  */
! #define EVR(N)		((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N))