From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27997 invoked by alias); 14 Jun 2004 20:06:30 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 27821 invoked from network); 14 Jun 2004 20:06:20 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org with SMTP; 14 Jun 2004 20:06:20 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i5EK6Hi5019538 for ; Mon, 14 Jun 2004 16:06:17 -0400 Received: from zenia.home.redhat.com (porkchop.devel.redhat.com [172.16.58.2]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i5EK6F009756; Mon, 14 Jun 2004 16:06:16 -0400 To: gdb-patches@sources.redhat.com Subject: RFA: sim: fix concatenation of E500 high / low gpr halves From: Jim Blandy Date: Mon, 14 Jun 2004 20:06:00 -0000 Message-ID: User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.3 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2004-06/txt/msg00322.txt.bz2 This fixes various failures in e500-regs.exp, in which the value assigned to evfoo.v2_int32[0] is always read back as 0xffffffff when evfoo.v2_int32[1] has its top bit set. 2004-06-14 Jim Blandy * e500_registers.h (EVR): Cast the 32-bit value of the GPR to an unsigned type before or-ing it with a 64-bit value. Index: sim/ppc/e500_registers.h =================================================================== RCS file: /cvs/src/src/sim/ppc/e500_registers.h,v retrieving revision 1.1 diff -c -p -r1.1 e500_registers.h *** sim/ppc/e500_registers.h 22 Jun 2003 16:48:12 -0000 1.1 --- sim/ppc/e500_registers.h 14 Jun 2004 20:03:06 -0000 *************** struct e500_regs { *** 79,83 **** /* e500 register high bits */ #define GPRH(N) cpu_registers(processor)->e500.gprh[N] ! /* e500 unified vector register */ ! #define EVR(N) ((((unsigned64)GPRH(N)) << 32) | GPR(N)) --- 79,86 ---- /* e500 register high bits */ #define GPRH(N) cpu_registers(processor)->e500.gprh[N] ! /* e500 unified vector register ! We need to cast the gpr value to an unsigned type so that it ! doesn't get sign-extended when it's or-ed with a 64-bit value; that ! would wipe out the upper 32 bits of the register's value. */ ! #define EVR(N) ((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N))