Re: [PATCH-ppc 5/5] Add VSX doc bits

[Eli Zaretskii <eliz@gnu.org>]

> From: Luis Machado <luisgpm@linux.vnet.ibm.com>
> Cc: Eli Zaretskii <eliz@gnu.org>
> Date: Fri, 15 Aug 2008 12:28:16 -0300
> 
> What do you think about the doc bits for this one?
> 
> Regards,
> > 2008-07-25  Luis Machado  <luisgpm@br.ibm.com>
> > 
> > 	* doc/gdb.texinfo: Updated documentation with new support info.	

This needs to state the node name where the changes are made.

> > 
> > Index: gdb/doc/gdb.texinfo
> > ===================================================================
> > --- gdb.orig/doc/gdb.texinfo	2008-07-23 09:28:06.000000000 -0700
> > +++ gdb/doc/gdb.texinfo	2008-07-23 09:31:44.000000000 -0700
> > @@ -16210,6 +16210,9 @@
> >  by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0},
> >  @code{f2} and @code{f3} for @code{$dl1} and so on.
> > 
> > +For POWER7 processors, GDB provides a new set of pseudo-registers, the 64-bit
> > +wide Extended Floating Point Registers (@samp{f32} through @samp{f63}).
> > +
> > 
> >  @node Controlling GDB
> >  @chapter Controlling @value{GDBN}
> > @@ -27406,6 +27409,13 @@
> >  contain registers @samp{vr0} through @samp{vr31}, @samp{vscr},
> >  and @samp{vrsave}.
> > 
> > +The @samp{org.gnu.gdb.power.vsx} feature is optional.  It should
> > +contain registers @samp{vs0h} through @samp{vs31h}.  @value{GDBN}
> > +will combine these registers with the floating point registers
> > +(@samp{f0} through @samp{f31}) and the altivec registers (@samp{vr0}
> > +through @samp{vr31}} to present the 128-bit wide registers @samp{vs0}
> > +through @samp{vs63}, the new set of vector registers for POWER7.
> > +

This is OK, modulo Stan's comments on using "new".