From: Alexandre Oliva <aoliva@redhat.com>
To: gdb-patches@sources.redhat.com
Subject: [patch] h8300 sim gets mul/div with imm wrong
Date: Sun, 27 Jun 2004 06:35:00 -0000 [thread overview]
Message-ID: <orzn6ppkzj.fsf@livre.redhat.lsd.ic.unicamp.br> (raw)
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The immediate operands passed to multiply and divide instructions are
all zero-extended to 16 or 32 bits. This patch fixes this problem.
While at that, I found another patch that we'd failed to contribute
before, that fixes a case of mova that is mishandled by the current
code.
Ok to install?
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Index: sim/h8300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2003-07-23 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Make sure that dst.reg refers to the
right register byte in mova/sz.l @(dd,RnL),ERn.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
mulxs, divs and divxs.
Index: sim/h8300/compile.c
===================================================================
RCS file: /cvs/uberbaum/./sim/h8300/compile.c,v
retrieving revision 1.40
diff -u -p -r1.40 compile.c
--- sim/h8300/compile.c 10 Jun 2004 20:22:17 -0000 1.40
+++ sim/h8300/compile.c 27 Jun 2004 06:27:22 -0000
@@ -2037,7 +2037,10 @@ sim_resume (SIM_DESC sd, int step, int s
code->op3.literal = 0;
if (OP_KIND (code->src.type) == OP_INDEXB)
- code->dst.type = X (OP_REG, SB);
+ {
+ code->dst.type = X (OP_REG, SB);
+ code->dst.reg = code->op3.reg + 8;
+ }
else
code->dst.type = X (OP_REG, SW);
}
@@ -3886,13 +3889,7 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfff0;
- else
- ea = SEXTSHORT (ea);
-
+ ea = SEXTSHORT (ea);
res = SEXTSHORT (ea * SEXTSHORT (rd));
n = res & 0x8000;
@@ -3907,11 +3904,6 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
-
res = ea * rd;
n = res & 0x80000000;
@@ -3925,11 +3917,6 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
-
/* Compute upper 32 bits of the 64-bit result. */
res = (((long long) ea) * ((long long) rd)) >> 32;
@@ -3985,13 +3972,7 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
- else
- ea = SEXTCHAR (ea);
-
+ ea = SEXTCHAR (ea);
res = ea * SEXTCHAR (rd);
n = res & 0x8000;
@@ -4006,13 +3987,7 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfff0;
- else
- ea = SEXTSHORT (ea);
-
+ ea = SEXTSHORT (ea);
res = ea * SEXTSHORT (rd & 0xffff);
n = res & 0x80000000;
@@ -4103,11 +4078,6 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
-
if (ea)
{
res = SEXTSHORT (rd) / SEXTSHORT (ea);
@@ -4129,11 +4099,6 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
-
if (ea)
{
res = rd / ea;
@@ -4205,13 +4170,7 @@ sim_resume (SIM_DESC sd, int step, int s
goto end;
rd = SEXTSHORT (rd);
-
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
- else
- ea = SEXTCHAR (ea);
+ ea = SEXTCHAR (ea);
if (ea)
{
@@ -4236,12 +4195,7 @@ sim_resume (SIM_DESC sd, int step, int s
fetch (sd, &code->dst, &rd))
goto end;
- /* FIXME: is this the right place to be doing sign extend? */
- if (OP_KIND (code->src.type) == OP_IMM &&
- (ea & 8) != 0)
- ea |= 0xfffffff0;
- else
- ea = SEXTSHORT (ea);
+ ea = SEXTSHORT (ea);
if (ea)
{
Index: sim/testsuite/sim/h8300/ChangeLog
from Alexandre Oliva <aoliva@redhat.com>
2003-07-22 Michael Snyder <msnyder@redhat.com>
* mul.s: Don't try to use negative immediate (it's always
unsigned).
* div.s: Ditto.
Index: sim/testsuite/sim/h8300/div.s
===================================================================
RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/div.s,v
retrieving revision 1.1
diff -u -p -r1.1 div.s
--- sim/testsuite/sim/h8300/div.s 19 Jun 2003 02:40:12 -0000 1.1
+++ sim/testsuite/sim/h8300/div.s 27 Jun 2004 06:27:23 -0000
@@ -41,9 +41,9 @@ divs_w_imm4_reg:
set_grs_a5a5
;; divs.w xx:4, rd
- mov.w #32, r1
+ mov.w #-32, r1
set_ccr_zero
- divs.w #-2:4, r1
+ divs.w #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
@@ -88,9 +88,9 @@ divs_l_imm4_reg:
set_grs_a5a5
;; divs.l xx:4, rd
- mov.l #320000, er1
+ mov.l #-320000, er1
set_ccr_zero
- divs.l #-2:4, er1
+ divs.l #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
@@ -221,9 +221,9 @@ divxs_b_imm4_reg:
set_grs_a5a5
;; divxs.b xx:4, rd
- mov.w #32, r1
+ mov.w #-32, r1
set_ccr_zero
- divxs.b #-2:4, r1
+ divxs.b #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
Index: sim/testsuite/sim/h8300/mul.s
===================================================================
RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/mul.s,v
retrieving revision 1.1
diff -u -p -r1.1 mul.s
--- sim/testsuite/sim/h8300/mul.s 19 Jun 2003 02:40:12 -0000 1.1
+++ sim/testsuite/sim/h8300/mul.s 27 Jun 2004 06:27:23 -0000
@@ -41,9 +41,9 @@ muls_w_imm4_reg:
set_grs_a5a5
;; muls.w xx:4, rd
- mov.w #32, r1
+ mov.w #-32, r1
set_ccr_zero
- muls.w #-2:4, r1
+ muls.w #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
@@ -88,9 +88,9 @@ muls_l_imm4_reg:
set_grs_a5a5
;; muls.l xx:4, rd
- mov.l #320000, er1
+ mov.l #-320000, er1
set_ccr_zero
- muls.l #-2:4, er1
+ muls.l #2:4, er1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
@@ -308,9 +308,9 @@ mulxs_b_imm4_reg:
set_grs_a5a5
;; mulxs.b xx:4, rd
- mov.w #32, r1
+ mov.w #-32, r1
set_ccr_zero
- mulxs.b #-2:4, r1
+ mulxs.b #2:4, r1
;; test ccr ; H=0 N=1 Z=0 V=0 C=0
test_neg_set
@@ -408,9 +408,9 @@ mulxu_b_imm4_reg:
set_grs_a5a5
;; mulxu.b xx:4, rd
- mov.b #32, r1l
+ mov.b #-32, r1l
set_ccr_zero
- mulxu.b #-2:4, r1
+ mulxu.b #2:4, r1
;; test ccr ; H=0 N=0 Z=0 V=0 C=0
test_cc_clear
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Alexandre Oliva http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org}
next reply other threads:[~2004-06-27 6:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-06-27 6:35 Alexandre Oliva [this message]
2004-06-28 14:52 ` Andrew Cagney
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