From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 13452 invoked by alias); 27 Jun 2004 06:35:14 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 13445 invoked from network); 27 Jun 2004 06:35:13 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org with SMTP; 27 Jun 2004 06:35:13 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i5R6ZDe1000868 for ; Sun, 27 Jun 2004 02:35:13 -0400 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i5R6ZD013241 for ; Sun, 27 Jun 2004 02:35:13 -0400 Received: from livre.redhat.lsd.ic.unicamp.br (vpn64-14.boston.redhat.com [172.16.66.14]) by pobox.corp.redhat.com (8.12.8/8.12.8) with ESMTP id i5R6ZBpI012319 for ; Sun, 27 Jun 2004 02:35:12 -0400 Received: from livre.redhat.lsd.ic.unicamp.br (livre.redhat.lsd.ic.unicamp.br [127.0.0.1]) by livre.redhat.lsd.ic.unicamp.br (8.12.11/8.12.11) with ESMTP id i5R6YfXU006555 for ; Sun, 27 Jun 2004 03:34:41 -0300 Received: (from aoliva@localhost) by livre.redhat.lsd.ic.unicamp.br (8.12.11/8.12.11/Submit) id i5R6YfpS006552; Sun, 27 Jun 2004 03:34:41 -0300 To: gdb-patches@sources.redhat.com Subject: [patch] h8300 sim gets mul/div with imm wrong From: Alexandre Oliva Organization: Red Hat Global Engineering Services Compiler Team Date: Sun, 27 Jun 2004 06:35:00 -0000 Message-ID: User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.3 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-=-=" X-SW-Source: 2004-06/txt/msg00592.txt.bz2 --=-=-= Content-length: 298 The immediate operands passed to multiply and divide instructions are all zero-extended to 16 or 32 bits. This patch fixes this problem. While at that, I found another patch that we'd failed to contribute before, that fixes a case of mova that is mishandled by the current code. Ok to install? --=-=-= Content-Type: text/x-patch Content-Disposition: inline; filename=sim-h8sx-muldiv-uimm.patch Content-length: 6753 Index: sim/h8300/ChangeLog from Alexandre Oliva 2003-07-23 Richard Sandiford * compile.c (sim_resume): Make sure that dst.reg refers to the right register byte in mova/sz.l @(dd,RnL),ERn. 2003-07-21 Richard Sandiford * compile.c (sim_resume): Zero-extend immediate to muls, mulsu, mulxs, divs and divxs. Index: sim/h8300/compile.c =================================================================== RCS file: /cvs/uberbaum/./sim/h8300/compile.c,v retrieving revision 1.40 diff -u -p -r1.40 compile.c --- sim/h8300/compile.c 10 Jun 2004 20:22:17 -0000 1.40 +++ sim/h8300/compile.c 27 Jun 2004 06:27:22 -0000 @@ -2037,7 +2037,10 @@ sim_resume (SIM_DESC sd, int step, int s code->op3.literal = 0; if (OP_KIND (code->src.type) == OP_INDEXB) - code->dst.type = X (OP_REG, SB); + { + code->dst.type = X (OP_REG, SB); + code->dst.reg = code->op3.reg + 8; + } else code->dst.type = X (OP_REG, SW); } @@ -3886,13 +3889,7 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfff0; - else - ea = SEXTSHORT (ea); - + ea = SEXTSHORT (ea); res = SEXTSHORT (ea * SEXTSHORT (rd)); n = res & 0x8000; @@ -3907,11 +3904,6 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - res = ea * rd; n = res & 0x80000000; @@ -3925,11 +3917,6 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - /* Compute upper 32 bits of the 64-bit result. */ res = (((long long) ea) * ((long long) rd)) >> 32; @@ -3985,13 +3972,7 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTCHAR (ea); - + ea = SEXTCHAR (ea); res = ea * SEXTCHAR (rd); n = res & 0x8000; @@ -4006,13 +3987,7 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfff0; - else - ea = SEXTSHORT (ea); - + ea = SEXTSHORT (ea); res = ea * SEXTSHORT (rd & 0xffff); n = res & 0x80000000; @@ -4103,11 +4078,6 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - if (ea) { res = SEXTSHORT (rd) / SEXTSHORT (ea); @@ -4129,11 +4099,6 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - if (ea) { res = rd / ea; @@ -4205,13 +4170,7 @@ sim_resume (SIM_DESC sd, int step, int s goto end; rd = SEXTSHORT (rd); - - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTCHAR (ea); + ea = SEXTCHAR (ea); if (ea) { @@ -4236,12 +4195,7 @@ sim_resume (SIM_DESC sd, int step, int s fetch (sd, &code->dst, &rd)) goto end; - /* FIXME: is this the right place to be doing sign extend? */ - if (OP_KIND (code->src.type) == OP_IMM && - (ea & 8) != 0) - ea |= 0xfffffff0; - else - ea = SEXTSHORT (ea); + ea = SEXTSHORT (ea); if (ea) { Index: sim/testsuite/sim/h8300/ChangeLog from Alexandre Oliva 2003-07-22 Michael Snyder * mul.s: Don't try to use negative immediate (it's always unsigned). * div.s: Ditto. Index: sim/testsuite/sim/h8300/div.s =================================================================== RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/div.s,v retrieving revision 1.1 diff -u -p -r1.1 div.s --- sim/testsuite/sim/h8300/div.s 19 Jun 2003 02:40:12 -0000 1.1 +++ sim/testsuite/sim/h8300/div.s 27 Jun 2004 06:27:23 -0000 @@ -41,9 +41,9 @@ divs_w_imm4_reg: set_grs_a5a5 ;; divs.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divs.w #-2:4, r1 + divs.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ divs_l_imm4_reg: set_grs_a5a5 ;; divs.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - divs.l #-2:4, er1 + divs.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -221,9 +221,9 @@ divxs_b_imm4_reg: set_grs_a5a5 ;; divxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - divxs.b #-2:4, r1 + divxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set Index: sim/testsuite/sim/h8300/mul.s =================================================================== RCS file: /cvs/uberbaum/./sim/testsuite/sim/h8300/mul.s,v retrieving revision 1.1 diff -u -p -r1.1 mul.s --- sim/testsuite/sim/h8300/mul.s 19 Jun 2003 02:40:12 -0000 1.1 +++ sim/testsuite/sim/h8300/mul.s 27 Jun 2004 06:27:23 -0000 @@ -41,9 +41,9 @@ muls_w_imm4_reg: set_grs_a5a5 ;; muls.w xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - muls.w #-2:4, r1 + muls.w #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -88,9 +88,9 @@ muls_l_imm4_reg: set_grs_a5a5 ;; muls.l xx:4, rd - mov.l #320000, er1 + mov.l #-320000, er1 set_ccr_zero - muls.l #-2:4, er1 + muls.l #2:4, er1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -308,9 +308,9 @@ mulxs_b_imm4_reg: set_grs_a5a5 ;; mulxs.b xx:4, rd - mov.w #32, r1 + mov.w #-32, r1 set_ccr_zero - mulxs.b #-2:4, r1 + mulxs.b #2:4, r1 ;; test ccr ; H=0 N=1 Z=0 V=0 C=0 test_neg_set @@ -408,9 +408,9 @@ mulxu_b_imm4_reg: set_grs_a5a5 ;; mulxu.b xx:4, rd - mov.b #32, r1l + mov.b #-32, r1l set_ccr_zero - mulxu.b #-2:4, r1 + mulxu.b #2:4, r1 ;; test ccr ; H=0 N=0 Z=0 V=0 C=0 test_cc_clear --=-=-= Content-length: 188 -- Alexandre Oliva http://www.ic.unicamp.br/~oliva/ Red Hat Compiler Engineer aoliva@{redhat.com, gcc.gnu.org} Free Software Evangelist oliva@{lsd.ic.unicamp.br, gnu.org} --=-=-=--