RFA: v850 simulator does not sign extend first operand to divh

[Nick Clifton <nickc@redhat.com>]

Hi Guys,

  May I apply the patch below please ?  It makes the v850 simulator
  sign extend its first operand, which is how the instruction should
  behave.

Cheers
        Nick

2003-04-03  Nick Clifton  <nickc@redhat.com>

	* simops.c (OP_40): Make divh sign extend its first operand.

Index: sim/v850/simops.c
===================================================================
RCS file: /cvs/src/src/sim/v850/simops.c,v
retrieving revision 1.6
diff -c -3 -p -w -r1.6 simops.c
*** sim/v850/simops.c	30 Nov 2002 18:01:30 -0000	1.6
--- sim/v850/simops.c	3 Apr 2003 07:28:28 -0000
*************** OP_6E0 ()
*** 775,788 ****
  int
  OP_40 ()
  {
!   unsigned int op0, op1, result, ov, s, z;
!   int temp;
  
    trace_input ("divh", OP_REG_REG, 0);
  
    /* Compute the result.  */
!   temp = EXTEND16 (State.regs[ OP[0] ]);
!   op0 = temp;
    op1 = State.regs[OP[1]];
    
    if (op0 == 0xffffffff && op1 == 0x80000000)
--- 775,787 ----
  int
  OP_40 ()
  {
!   boolean ov, s, z;
!   signed long int op0, op1, result;
  
    trace_input ("divh", OP_REG_REG, 0);
  
    /* Compute the result.  */
!   op0 = EXTEND16 (State.regs[ OP[0] ]);
    op1 = State.regs[OP[1]];
    
    if (op0 == 0xffffffff && op1 == 0x80000000)