From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23024 invoked by alias); 3 Apr 2003 07:29:53 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 23017 invoked from network); 3 Apr 2003 07:29:52 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 3 Apr 2003 07:29:52 -0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.11.6/8.11.6) with ESMTP id h337Tqe10241 for ; Thu, 3 Apr 2003 02:29:52 -0500 Received: from pobox.corp.redhat.com (pobox.corp.redhat.com [172.16.52.156]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h337TqJ01678 for ; Thu, 3 Apr 2003 02:29:52 -0500 Received: from workshop.nickc.cambridge.redhat.com.redhat.com (vpn50-9.rdu.redhat.com [172.16.50.9]) by pobox.corp.redhat.com (8.11.6/8.11.6) with ESMTP id h337Tnf10044 for ; Thu, 3 Apr 2003 02:29:51 -0500 To: gdb-patches@sources.redhat.com Subject: RFA: v850 simulator does not sign extend first operand to divh From: Nick Clifton Date: Thu, 03 Apr 2003 07:29:00 -0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-SW-Source: 2003-04/txt/msg00049.txt.bz2 Hi Guys, May I apply the patch below please ? It makes the v850 simulator sign extend its first operand, which is how the instruction should behave. Cheers Nick 2003-04-03 Nick Clifton * simops.c (OP_40): Make divh sign extend its first operand. Index: sim/v850/simops.c =================================================================== RCS file: /cvs/src/src/sim/v850/simops.c,v retrieving revision 1.6 diff -c -3 -p -w -r1.6 simops.c *** sim/v850/simops.c 30 Nov 2002 18:01:30 -0000 1.6 --- sim/v850/simops.c 3 Apr 2003 07:28:28 -0000 *************** OP_6E0 () *** 775,788 **** int OP_40 () { ! unsigned int op0, op1, result, ov, s, z; ! int temp; trace_input ("divh", OP_REG_REG, 0); /* Compute the result. */ ! temp = EXTEND16 (State.regs[ OP[0] ]); ! op0 = temp; op1 = State.regs[OP[1]]; if (op0 == 0xffffffff && op1 == 0x80000000) --- 775,787 ---- int OP_40 () { ! boolean ov, s, z; ! signed long int op0, op1, result; trace_input ("divh", OP_REG_REG, 0); /* Compute the result. */ ! op0 = EXTEND16 (State.regs[ OP[0] ]); op1 = State.regs[OP[1]]; if (op0 == 0xffffffff && op1 == 0x80000000)