[PATCH 0/3] RISC-V fflags, frm, and fcsr (includes small tdesc change)

[Andrew Burgess via Gdb-patches <gdb-patches@sourceware.org>]

While testing on a RISC-V native Linux target, I noticed some issues
accessing the fflags and frm registers.  This series addresses these issues.

Patch #2 is a small extension to the target description mechanism
required to support patch #3.

Thanks,
Andrew

---

Andrew Burgess (3):
  gdb/riscv: improve (and fix) display of frm field in 'info registers'
  gdb: Add tdesc_found_register function to tdesc API
  gdb/riscv: better support for fflags and frm registers

 gdb/arch/riscv.h                              |  19 +-
 gdb/features/riscv/32bit-fpu.c                |   4 +-
 gdb/features/riscv/32bit-fpu.xml              |   2 -
 gdb/features/riscv/64bit-fpu.c                |   4 +-
 gdb/features/riscv/64bit-fpu.xml              |   2 -
 gdb/riscv-tdep.c                              | 236 +++++++++++++++---
 gdb/riscv-tdep.h                              |   6 +
 gdb/target-descriptions.c                     |  11 +
 gdb/target-descriptions.h                     |   4 +
 gdb/testsuite/gdb.arch/riscv-info-fcsr.c      |  22 ++
 gdb/testsuite/gdb.arch/riscv-info-fcsr.exp    | 149 +++++++++++
 .../gdb.arch/riscv-tdesc-fcsr-32.xml          |  75 ++++++
 .../gdb.arch/riscv-tdesc-fcsr-64.xml          |  79 ++++++
 .../gdb.arch/riscv-tdesc-loading-05.xml       |  77 ++++++
 .../gdb.arch/riscv-tdesc-loading-06.xml       |  75 ++++++
 gdb/testsuite/gdb.arch/riscv-tdesc-regs.exp   |  36 +++
 16 files changed, 755 insertions(+), 46 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-info-fcsr.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-info-fcsr.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-fcsr-32.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-fcsr-64.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-05.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-tdesc-loading-06.xml

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2.25.4