From: Oleg Endo <olegendo1024@gmail.com>
To: Simon Marchi <simark@simark.ca>, gdb-patches@sourceware.org
Subject: Re: [SH] Check FPSCR.PR for fldi0, fldi1 insns in simulator
Date: Sun, 02 Aug 2026 22:42:45 +0900 [thread overview]
Message-ID: <b7904a1393f2a87b0e941488edbf2a61ed4b8363.camel@gmail.com> (raw)
In-Reply-To: <1ca6adbf81c1e1eabeb3360d99a1e92b0f450604.camel@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2245 bytes --]
Hi,
On Tue, 2026-03-17 at 13:50 +0900, Oleg Endo wrote:
>
> On Mon, 2026-03-16 at 21:19 -0400, Simon Marchi wrote:
> >
> > On 2026-03-16 21:18, Oleg Endo wrote:
> > > On Wed, 2026-03-11 at 10:39 -0400, Simon Marchi wrote:
> > > >
> > > > Ok, well since we're in "undefined behavior" territory we could argue
> > > > that the current sim behavior is fine. But I think the patch is still
> > > > good, traping is a more useful behavior to catch something you don't
> > > > want to happen.
> > >
> > > Yes, the current sim behavior is not wrong per se. But like you said,
> > > having it trap is more useful for sim's main purpose -- pre-verifying code.
> > >
> > >
> > > > > > The patch LGTM, but I am not a maintainer of the sim, so:
> > > > > >
> > > > > > Reviewed-By: Simon Marchi <simon.marchi@efficios.com>
> > > > > >
> > > > > > One note, please put the relevant information (the body of your email)
> > > > > > into the commit log itself).
> > > > >
> > > > > Yeah, sure I can expand the comment of the commit. Updated patch/commit
> > > > > attached.
> > > >
> > > > I would give it a week for Andrew or Mike to review and approve, but
> > > > otherwise I would feel comfortable merging it.
> > > >
> > >
> > > Alright. Last time I've checked I had write access. I can commit & push it
> > > myself. Just let me know.
> >
> > Yes, please go ahead.
> >
> >
>
> Thanks. Committed & pushed as 17eb89e3c1cc6098f08e77d257468486a5c04ce4.
>
This is a little late, but better than never.
I've just noticed that running
make check RUNTESTFLAGS="sh.exp"
in the sim build dir throws the following errors:
FAIL: sh fabs.s (execution)
FAIL: sh fadd.s (execution)
FAIL: sh fcmpeq.s (execution)
FAIL: sh fcmpgt.s (execution)
FAIL: sh fcnvsd.s (execution)
FAIL: sh float.s (execution)
FAIL: sh fmov.s (execution)
FAIL: sh fmul.s (execution)
FAIL: sh fneg.s (execution)
FAIL: sh fsqrt.s (execution)
FAIL: sh fsub.s (execution)
FAIL: sh ftrc.s (execution)
The behavior is correct and as expected. The test cases need to be adjusted
to match the fli0/fldi1 behavior. The attached patch fixes this.
OK to commit & push?
Best regards,
Oleg Endo
[-- Attachment #2: 0001-simsh-Fix-test-cases-after-flid0flid1-change-in-17eb89e3c1cc60.patch --]
[-- Type: text/x-patch, Size: 9249 bytes --]
From 121e27614329d3e6df97b030dbc92bf783f6eb11 Mon Sep 17 00:00:00 2001
From: Oleg Endo <olegendo@gcc.gnu.org>
Date: Sun, 2 Aug 2026 22:26:54 +0900
Subject: [PATCH] sim/sh: Fix test cases after flid0/flid1 change in 17eb89e3c1cc60
The previous change in 17eb89e3c1cc60 causes the sh sim fp tests to fail:
FAIL: sh fabs.s (execution)
FAIL: sh fadd.s (execution)
FAIL: sh fcmpeq.s (execution)
FAIL: sh fcmpgt.s (execution)
FAIL: sh fcnvsd.s (execution)
FAIL: sh float.s (execution)
FAIL: sh fmov.s (execution)
FAIL: sh fmul.s (execution)
FAIL: sh fneg.s (execution)
FAIL: sh fsqrt.s (execution)
FAIL: sh fsub.s (execution)
FAIL: sh ftrc.s (execution)
The behavior is correct and as expected. The test cases need to be adjusted
to match the fli0/fldi1 behavior.
---
sim/testsuite/sh/fabs.s | 11 ++++++++++-
sim/testsuite/sh/fadd.s | 3 ++-
sim/testsuite/sh/fcmpeq.s | 11 ++++++++---
sim/testsuite/sh/fcmpgt.s | 11 ++++++++---
sim/testsuite/sh/fcnvsd.s | 3 ++-
sim/testsuite/sh/float.s | 4 ++--
sim/testsuite/sh/fmov.s | 1 +
sim/testsuite/sh/fmul.s | 2 +-
sim/testsuite/sh/fneg.s | 11 +++++++++--
sim/testsuite/sh/fsqrt.s | 13 ++++++++++---
sim/testsuite/sh/fsub.s | 17 +++++++++++++++--
sim/testsuite/sh/ftrc.s | 7 ++++---
12 files changed, 72 insertions(+), 22 deletions(-)
diff --git a/sim/testsuite/sh/fabs.s b/sim/testsuite/sh/fabs.s
index 1fb354e..e6b68b5 100644
--- a/sim/testsuite/sh/fabs.s
+++ b/sim/testsuite/sh/fabs.s
@@ -55,40 +55,49 @@ fabs_dreg_b0:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
- double_prec
# fabs(0.0) = 0.0.
+ single_prec
fldi0 fr0
+ double_prec
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 0 dr0
# fabs(1.0) = 1.0.
+ single_prec
fldi1 fr0
+ double_prec
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
+ single_prec
fldi1 fr2
+ double_prec
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L4
fail
.L4:
# fabs(-1.0) = 1.0.
+ single_prec
fldi1 fr0
+ double_prec
fneg fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
+ single_prec
fldi1 fr2
+ double_prec
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
diff --git a/sim/testsuite/sh/fadd.s b/sim/testsuite/sh/fadd.s
index 72431f0..5895e36 100644
--- a/sim/testsuite/sh/fadd.s
+++ b/sim/testsuite/sh/fadd.s
@@ -44,9 +44,10 @@ fadd_freg_freg_b0:
fadd_dreg_dreg_b0:
set_grs_a5a5
set_fprs_a5a5
- double_prec
+ single_prec
fldi1 fr0
fldi1 fr2
+ double_prec
flds fr0, fpul
fcnvsd fpul, dr0
flds fr2, fpul
diff --git a/sim/testsuite/sh/fcmpeq.s b/sim/testsuite/sh/fcmpeq.s
index 9c0ef57..5bebae2 100644
--- a/sim/testsuite/sh/fcmpeq.s
+++ b/sim/testsuite/sh/fcmpeq.s
@@ -59,39 +59,44 @@ fcmpeq_double:
# 1.0 == 1.0
set_grs_a5a5
set_fprs_a5a5
- double_prec
+ single_prec
fldi1 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# 0.0 != 1.0
+ single_prec
fldi0 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L11
fail
.L11:
# 1.0 != 0.0
+ single_prec
fldi1 fr0
fldi0 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L12
fail
.L12:
# 2.0 != 1.0
- fldi1 fr0
single_prec
+ fldi1 fr0
fadd fr0, fr0
- double_prec
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
diff --git a/sim/testsuite/sh/fcmpgt.s b/sim/testsuite/sh/fcmpgt.s
index c6945ba..d631f94 100644
--- a/sim/testsuite/sh/fcmpgt.s
+++ b/sim/testsuite/sh/fcmpgt.s
@@ -59,40 +59,45 @@ fcmpgt_double:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
- double_prec
# 1.0 !> 1.0.
+ single_prec
fldi1 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L10
fail
.L10:
# 0.0 !> 1.0.
+ single_prec
fldi0 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bt .L11
fail
.L11:
# 1.0 > 0.0.
+ single_prec
fldi1 fr0
fldi0 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L12
fail
.L12:
# 2.0 > 1.0.
- fldi1 fr0
single_prec
+ fldi1 fr0
fadd fr0, fr0
- double_prec
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
diff --git a/sim/testsuite/sh/fcnvsd.s b/sim/testsuite/sh/fcnvsd.s
index 6592540..3c56236 100644
--- a/sim/testsuite/sh/fcnvsd.s
+++ b/sim/testsuite/sh/fcnvsd.s
@@ -7,8 +7,9 @@
start
set_grs_a5a5
set_fprs_a5a5
- double_prec
+ single_prec
fldi1 fr0
+ double_prec
flds fr0, fpul
fcnvsd fpul, dr2
assert_dpreg_i 1, dr2
diff --git a/sim/testsuite/sh/float.s b/sim/testsuite/sh/float.s
index e5a3bc6..3e88640 100644
--- a/sim/testsuite/sh/float.s
+++ b/sim/testsuite/sh/float.s
@@ -81,9 +81,9 @@ double_pos:
float fpul, dr4
# check the result.
+ single_prec
fldi1 fr0
fldi1 fr1
- single_prec
fadd fr0, fr1
fadd fr0, fr1
double_prec
@@ -100,9 +100,9 @@ double_neg:
float fpul, dr4
# check the result.
+ single_prec
fldi1 fr0
fldi1 fr1
- single_prec
fadd fr0, fr1
fadd fr0, fr1
fneg fr1
diff --git a/sim/testsuite/sh/fmov.s b/sim/testsuite/sh/fmov.s
index 29c51b5..d08fc4d 100644
--- a/sim/testsuite/sh/fmov.s
+++ b/sim/testsuite/sh/fmov.s
@@ -5,6 +5,7 @@
.include "testutils.inc"
.macro init
+ single_prec
fldi0 fr0
fldi1 fr1
fldi1 fr2
diff --git a/sim/testsuite/sh/fmul.s b/sim/testsuite/sh/fmul.s
index 81a2545..4e140b9 100644
--- a/sim/testsuite/sh/fmul.s
+++ b/sim/testsuite/sh/fmul.s
@@ -59,10 +59,10 @@ fmul_single:
test_fpr_a5a5 fr15
.macro dinit
+ single_prec
fldi0 fr0
fldi1 fr2
fldi1 fr4
- single_prec
fadd fr4, fr4
double_prec
_s2d fr0, dr0
diff --git a/sim/testsuite/sh/fneg.s b/sim/testsuite/sh/fneg.s
index dd5fe5d..1ec56d3 100644
--- a/sim/testsuite/sh/fneg.s
+++ b/sim/testsuite/sh/fneg.s
@@ -56,35 +56,42 @@ fneg_single:
fneg_double:
set_grs_a5a5
set_fprs_a5a5
- double_prec
# neg(0.0) = 0.0.
+ single_prec
fldi0 fr0
fldi0 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fneg dr0
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# neg(1.0) = fsub(0,1)
+ single_prec
fldi1 fr0
+ double_prec
_s2d fr0, dr0
fneg dr0
+ single_prec
fldi0 fr2
fldi1 fr3
- single_prec
fsub fr3, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# neg(neg(1.0)) = 1.0.
+ single_prec
fldi1 fr0
+ double_prec
_s2d fr0, dr0
+ single_prec
fldi1 fr2
+ double_prec
_s2d fr2, dr2
fneg dr2
fneg dr2
diff --git a/sim/testsuite/sh/fsqrt.s b/sim/testsuite/sh/fsqrt.s
index cb61bcf..5c29c30 100644
--- a/sim/testsuite/sh/fsqrt.s
+++ b/sim/testsuite/sh/fsqrt.s
@@ -57,42 +57,49 @@ fsqrt_single:
test_fpr_a5a5 fr15
fsqrt_double:
- double_prec
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
+ single_prec
fldi0 fr0
+ double_prec
_s2d fr0, dr0
fsqrt dr0
+ single_prec
fldi0 fr2
+ double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# sqrt(1.0) = 1.0.
+ single_prec
fldi1 fr0
+ double_prec
_s2d fr0, dr0
fsqrt dr0
+ single_prec
fldi1 fr2
+ double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# sqrt(4.0) = 2.0.
+ single_prec
fldi1 fr0
# Double it.
- single_prec
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
double_prec
_s2d fr0, dr0
fsqrt dr0
+ single_prec
fldi1 fr2
# Double it.
- single_prec
fadd fr2, fr2
double_prec
_s2d fr2, dr2
diff --git a/sim/testsuite/sh/fsub.s b/sim/testsuite/sh/fsub.s
index dfe9172..1d13a63 100644
--- a/sim/testsuite/sh/fsub.s
+++ b/sim/testsuite/sh/fsub.s
@@ -66,51 +66,64 @@ fsub_single:
fsub_double:
set_grs_a5a5
set_fprs_a5a5
- double_prec
# 0.0 - 0.0 = 0.0.
+ single_prec
fldi0 fr0
fldi0 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
+ single_prec
fldi0 fr4
+ double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L10
fail
.L10:
# 1.0 - 0.0 = 1.0.
+ single_prec
fldi0 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
+ single_prec
fldi1 fr4
+ double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L11
fail
.L11:
# 1.0 - 1.0 = 0.0.
+ single_prec
fldi1 fr0
fldi1 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
+ single_prec
fldi0 fr4
+ double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L12
fail
.L12:
# 0.0 - 1.0 = -1.0.
+ single_prec
fldi1 fr0
fldi0 fr2
+ double_prec
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
- fldi1 fr4
single_prec
+ fldi1 fr4
fneg fr4
double_prec
_s2d fr4, dr4
diff --git a/sim/testsuite/sh/ftrc.s b/sim/testsuite/sh/ftrc.s
index 25e33be..ac11600 100644
--- a/sim/testsuite/sh/ftrc.s
+++ b/sim/testsuite/sh/ftrc.s
@@ -59,9 +59,10 @@ ftrc_single:
fail
ftrc_double:
- double_prec
# ftrc(0.0) = 0.
+ single_prec
fldi0 fr0
+ double_prec
_s2d fr0, dr0
ftrc dr0, fpul
# check results.
@@ -72,11 +73,11 @@ ftrc_double:
fail
.L10:
# ftrc(1.5) = 1.
+ single_prec
fldi1 fr0
fldi1 fr2
fldi1 fr4
# double it.
- single_prec
fadd fr4, fr4
# form 0.5.
fdiv fr4, fr2
@@ -97,11 +98,11 @@ ftrc_double:
fail
.L11:
# ftrc(-1.5) = -1.
+ single_prec
fldi1 fr0
fneg fr0
fldi1 fr2
fldi1 fr4
- single_prec
# double it.
fadd fr4, fr4
# form the fraction.
--
libgit2 1.9.0
next prev parent reply other threads:[~2026-08-02 13:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 3:02 Oleg Endo
2026-03-11 4:27 ` Simon Marchi
2026-03-11 6:20 ` Oleg Endo
2026-03-11 14:39 ` Simon Marchi
2026-03-17 1:18 ` Oleg Endo
2026-03-17 1:19 ` Simon Marchi
2026-03-17 4:50 ` Oleg Endo
2026-08-02 13:42 ` Oleg Endo [this message]
2026-08-24 11:03 ` Ping^1 " Oleg Endo
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