Re: [PATCH] RISC-V: support for vector register accesses via ptrace() in RISC-V Linux native

[Heinrich Schuchardt <heinrich.schuchardt@canonical.com>]

On 9/12/26 09:37, Heinrich Schuchardt wrote:
>> +      if (regnum == RISCV_CSR_VXRM_REGNUM)
>> +    {
>> +      /* Overwrite VCSR with the VXRM bit here.  */
>> +          gdb_byte *buf = (gdb_byte *) &vxsat_from_regcache;

I guess the typo is here

%s/vxsat_from_regcache/vxrm_from_regcache/

Best regards

Heinrich

>> +      regcache->raw_collect (RISCV_CSR_VXRM_REGNUM, buf);
>> +      vregs->vstate.vcsr &= ~((uint64_t) VCSR_MASK_VXRM << 
>> VCSR_POS_VXRM);
>> +      vregs->vstate.vcsr |= ((vxrm_from_regcache & VCSR_MASK_VXRM)
>> +              << VCSR_POS_VXRM);
> 
> vxrm_from_regcache is never initialized. So you are using a random value 
> from the stack. Can we completely remove the variable?