From: "Maciej W. Rozycki" <macro@orcam.me.uk>
To: Kirill Radkin <hokeygo@gmail.com>
Cc: gdb-patches@sourceware.org,
Peter Bergner <bergner@oss.tenstorrent.com>,
Sergey Matyukevich <geomatsi@gmail.com>,
Jerry Zhang Jian <jerry.zhangjian@sifive.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Andrew Burgess <aburgess@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 1/3] RISC-V Vector Extension Support
Date: Wed, 14 Oct 2026 04:21:54 +0100 (BST) [thread overview]
Message-ID: <alpine.DEB.2.21.2610140409030.55767@angie.orcam.me.uk> (raw)
In-Reply-To: <20260925172947.403655-2-hokeygo@gmail.com>
On Fri, 25 Sep 2026, Kirill Radkin wrote:
> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
> index 1443bc20a7d..0261d4d0f9e 100644
> --- a/gdb/arch/riscv.h
> +++ b/gdb/arch/riscv.h
> @@ -51,7 +51,7 @@ struct riscv_gdbarch_features
> target should be 16 and 4 for an embedded subset compliant target (with
> 'Zve32*' extension), but GDB doesn't currently mind, and will accept any
> vector size. */
> - int vlen = 0;
> + int vlenb = 0;
What's the rationale behind the member rename? If this is legitimate,
then can you please submit a preparatory change that does only the rename
without mixing it with new code, which only causes obfuscation?
> @@ -68,9 +68,8 @@ struct riscv_gdbarch_features
> /* Equality operator. */
> bool operator== (const struct riscv_gdbarch_features &rhs) const
> {
> - return (xlen == rhs.xlen && flen == rhs.flen
> - && embedded == rhs.embedded && vlen == rhs.vlen
> - && has_fflags_reg == rhs.has_fflags_reg
> + return (xlen == rhs.xlen && flen == rhs.flen && embedded == rhs.embedded
> + && vlenb == rhs.vlenb && has_fflags_reg == rhs.has_fflags_reg
> && has_frm_reg == rhs.has_frm_reg
> && has_fcsr_reg == rhs.has_fcsr_reg);
> }
> @@ -84,13 +83,10 @@ struct riscv_gdbarch_features
> /* Used by std::unordered_map to hash feature sets. */
> std::size_t hash () const noexcept
> {
> - std::size_t val = ((embedded ? 1 : 0) << 10
> - | (has_fflags_reg ? 1 : 0) << 11
> - | (has_frm_reg ? 1 : 0) << 12
> - | (has_fcsr_reg ? 1 : 0) << 13
> - | (xlen & 0x1f) << 5
> - | (flen & 0x1f) << 0
> - | (vlen & 0x3fff) << 14);
> + std::size_t val
> + = ((embedded ? 1 : 0) << 10 | (has_fflags_reg ? 1 : 0) << 11
> + | (has_frm_reg ? 1 : 0) << 12 | (has_fcsr_reg ? 1 : 0) << 13
> + | (xlen & 0x1f) << 5 | (flen & 0x1f) << 0 | (vlenb & 0x3fff) << 14);
The only functional change here is AFAICT s/vlen/vlenb/ and the rest is
reformatting, which obfuscates the update. Would you then please remove
the formatting changes and if you indeed think they're needed, then submit
them as a follow-up cleanup?
I'll yet see if I can look through the rest of your changes, but this
just stood out prominently for me.
Maciej
next prev parent reply other threads:[~2026-10-14 3:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 17:29 [PATCH v2 0/3] RISC-V Vector Extension support Kirill Radkin
2026-09-25 17:29 ` [PATCH v2 1/3] RISC-V Vector Extension Support Kirill Radkin
2026-10-08 19:44 ` Andrew Burgess
2026-10-08 19:52 ` Jerry Zhang Jian
2026-10-13 13:58 ` Andrew Burgess
2026-10-13 14:19 ` Jerry Zhang Jian
2026-10-14 3:21 ` Maciej W. Rozycki [this message]
2026-09-25 17:29 ` [PATCH v2 2/3] Reverse execution support for RISC-V Vector Extension Kirill Radkin
2026-09-25 17:29 ` [PATCH v2 3/3] RISC-V Vector Extension Support Testing Kirill Radkin
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