[PATCH v2 0/3] RISC-V Vector Extension support

[Kirill Radkin <hokeygo@gmail.com>]

Hi all,

This series adds RISC-V Vector Extension support to native Linux GDB and
gdbserver. It provides access to v0-v31 and the vector CSRs, target
descriptions sized according to VLENB, and support for the vector calling
convention in inferior calls.

It also contains a separate RVV instruction-recording patch for reverse
execution and tests covering register access, CSR printing, and vector and
tuple arguments and return values. The RVV support has been tested at VLEN
values of 64, 128, and 1024, using both system QEMU on Linux and an
OpenOCD + Spike setup.

Jerry Zhang Jian pointed out in an earlier message that the Tcl procedures
needed by the tests were missing. They are now included.

I am continuing to work on this series and plan to send further improvements.

I've CCed Andrew and Palmer since they are listed as RISC-V maintainers in
gdb/MAINTAINERS, and Peter Bergner, Sergey Matyukevich, Jerry Zhang Jian,
and Heinrich Schuchardt because of earlier discussion of this work.

Best regards,
Kirill

Kirill Radkin (3):
  RISC-V Vector Extension Support
  Reverse execution support for RISC-V Vector Extension
  RISC-V Vector Extension Support Testing

 gdb/arch/riscv.c                              |    9 +-
 gdb/arch/riscv.h                              |   18 +-
 gdb/features/riscv/rvv.c                      |  113 ++
 gdb/gdbtypes.c                                |   41 +
 gdb/nat/riscv-linux-ptrace.h                  |   31 +
 gdb/nat/riscv-linux-tdesc.c                   |   35 +
 gdb/riscv-linux-nat.c                         |  164 ++
 gdb/riscv-regs.h                              |   79 +
 gdb/riscv-tdep.c                              | 1369 ++++++++++++++++-
 gdb/riscv-tdep.h                              |   63 +-
 ...iscv-vector-abi-full-generate-template.txt |  176 +++
 .../riscv-vector-abi-full-generate.py         |  384 +++++
 .../gdb.arch/riscv-vector-abi-full.c          |   23 +
 .../gdb.arch/riscv-vector-abi-full.exp        |   72 +
 gdb/testsuite/gdb.arch/riscv-vector-abi.c     |  157 ++
 gdb/testsuite/gdb.arch/riscv-vector-abi.exp   |  247 +++
 .../gdb.arch/riscv-vu-availability.c          |   67 +
 .../gdb.arch/riscv-vu-availability.exp        |   72 +
 .../gdb.arch/riscv-vu-consitency-checks.c     |   79 +
 .../gdb.arch/riscv-vu-consitency-checks.exp   |  156 ++
 gdb/testsuite/gdb.arch/riscv-vu-ctx-print.c   |  106 ++
 gdb/testsuite/gdb.arch/riscv-vu-ctx-print.exp |  107 ++
 gdb/testsuite/gdb.arch/riscv-vu-printout.c    |   69 +
 gdb/testsuite/gdb.arch/riscv-vu-printout.exp  |   92 ++
 .../gdb.arch/riscv-vu-rvv-unsupported.c       |   23 +
 .../gdb.arch/riscv-vu-rvv-unsupported.exp     |   46 +
 gdb/testsuite/gdb.arch/riscv-vu-rwr.c         |   62 +
 gdb/testsuite/gdb.arch/riscv-vu-rwr.exp       |  173 +++
 .../gdb.arch/riscv-vu-side-effects.c          |   86 ++
 .../gdb.arch/riscv-vu-side-effects.exp        |  162 ++
 gdb/testsuite/lib/gdb.exp                     |  124 ++
 gdb/testsuite/lib/riscv64-rvv-lib.exp         |  347 +++++
 gdbserver/linux-riscv-low.cc                  |  129 +-
 gdbsupport/common-utils.h                     |   22 +
 include/opcode/riscv-opc.h                    |   79 +
 include/opcode/riscv.h                        |   10 +
 36 files changed, 4832 insertions(+), 160 deletions(-)
 create mode 100644 gdb/features/riscv/rvv.c
 create mode 100644 gdb/nat/riscv-linux-ptrace.h
 create mode 100644 gdb/riscv-regs.h
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi-full-generate-template.txt
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi-full-generate.py
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi-full.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi-full.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vector-abi.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-availability.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-availability.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-consitency-checks.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-consitency-checks.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-ctx-print.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-ctx-print.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-printout.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-printout.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-rvv-unsupported.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-rvv-unsupported.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-rwr.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-rwr.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-side-effects.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-vu-side-effects.exp
 create mode 100644 gdb/testsuite/lib/riscv64-rvv-lib.exp


base-commit: ba3e439f17aabdb5b1a9ca61646f9c22604ab259
-- 
2.43.0