Re: [PATCH] [PATCH v3] RISC-V: support for vector register accesses via ptrace() in RISC-V Linux native

[Charlie Jenkins <charlie@rivosinc.com>]

On Mon, Apr 28, 2025 at 06:12:16PM +0100, Andrew Burgess wrote:
> Charlie Jenkins <charlie@rivosinc.com> writes:
> 
> > On Thu, Apr 24, 2025 at 12:19:14PM +0000, snatu@whileone.in wrote:
> >> From: Sameer Natu <snatu@whileone.in>
> >> 
> >> A v3 re-spin of the original patch.
> >> Tested with latest kernel 6.14.2 on RISCV QEMU.
> >> Removed Magic Numbers from v2 patch and worked on review comments of v2 patch.
> >
> > Thanks for working on this!
> >
> > Can you add a co-developed-by tag for the original author?
> >
> > You also don't need to have [PATCH] twice in the header!
> >
> > There are a handful of erroneous spaces at the end of lines.
> >
> > I tested this patch and I noticed that the vector instructions are not
> > being decoded.
> >
> > Breakpoint 1, vector () at main.S:4
> > 4               vsetvli t0, a0, e32, m4, ta, ma
> > 1: x/i $pc
> > => 0x55555555566c <vector>:     .insn   4, 0x0d2572d
> 
> Does an `objdump` built from the same tree decode these instructions?
> Wondering if this is a problem with the objdump disassembler library, or
> a problem with the way GDB uses that library.

Yes, `objdump -d` from the same tree dumps the instruction. Perhaps some
entry needs to be added to `riscv_gdbarch_init()` in gdb/riscv-tdep.c?

- Charlie

> 
> Thanks,
> Andrew
>