From: Mike Frysinger <vapier@gentoo.org>
To: jaydeep.patil@imgtec.com
Cc: gdb-patches@sourceware.org, aburgess@redhat.com,
joseph.faulls@imgtec.com, bhushan.attarde@imgtec.com
Subject: Re: [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation
Date: Mon, 18 Dec 2023 11:29:38 -0500 [thread overview]
Message-ID: <ZYBzcgsO1NJrL6Y-@vapier> (raw)
In-Reply-To: <20231217065218.3799535-3-jaydeep.patil@imgtec.com>
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On 17 Dec 2023 06:52, jaydeep.patil@imgtec.com wrote:
> Added support for compressed integer instruction set ("c").
you haven't responded to feedback in previous patches. please do that
before posting new ones, or clearly document in the patch the feedback
you've addressed as is standard git behavior.
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
>
> +/* Return address register. */
> +#define REG_RA 1
> +
> +/* Stack pointer register. */
> +#define REG_SP 2
we already have SIM_RISCV_xxx_REGNUM. don't invent new ones.
-mike
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next prev parent reply other threads:[~2023-12-18 16:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-17 6:52 [PATCH v3 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support jaydeep.patil
2023-12-17 6:52 ` [PATCH v3 1/3] [sim/riscv] Fix crash during instruction decoding jaydeep.patil
2023-12-18 16:26 ` Mike Frysinger
2023-12-19 6:14 ` [EXTERNAL] " Jaydeep Patil
2023-12-17 6:52 ` [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation jaydeep.patil
2023-12-18 16:29 ` Mike Frysinger [this message]
2023-12-19 6:15 ` [EXTERNAL] " Jaydeep Patil
2023-12-17 6:52 ` [PATCH v3 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-12-18 16:30 ` Mike Frysinger
2023-12-19 6:16 ` [EXTERNAL] " Jaydeep Patil
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