From: Mike Frysinger <vapier@gentoo.org>
To: jaydeep.patil@imgtec.com
Cc: gdb-patches@sourceware.org, aburgess@redhat.com,
joseph.faulls@imgtec.com, bhushan.attarde@imgtec.com
Subject: Re: [PATCH v3 1/3] [sim/riscv] Fix crash during instruction decoding
Date: Mon, 18 Dec 2023 11:26:52 -0500 [thread overview]
Message-ID: <ZYByzMswkYvuLmOV@vapier> (raw)
In-Reply-To: <20231217065218.3799535-2-jaydeep.patil@imgtec.com>
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On 17 Dec 2023 06:52, jaydeep.patil@imgtec.com wrote:
> The match_never() function has been removed and thus step_once() crashes
> during instruction decoding. Fixed it by checking for null pointer before
> invoking function attached to match_func member of riscv_opcode structure.
the opcodes code is still doing:
if (! (op->match_func) (op, word))
-mike
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next prev parent reply other threads:[~2023-12-18 16:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-17 6:52 [PATCH v3 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support jaydeep.patil
2023-12-17 6:52 ` [PATCH v3 1/3] [sim/riscv] Fix crash during instruction decoding jaydeep.patil
2023-12-18 16:26 ` Mike Frysinger [this message]
2023-12-19 6:14 ` [EXTERNAL] " Jaydeep Patil
2023-12-17 6:52 ` [PATCH v3 2/3] [sim/riscv] Add support for compressed integer instruction set simulation jaydeep.patil
2023-12-18 16:29 ` Mike Frysinger
2023-12-19 6:15 ` [EXTERNAL] " Jaydeep Patil
2023-12-17 6:52 ` [PATCH v3 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-12-18 16:30 ` Mike Frysinger
2023-12-19 6:16 ` [EXTERNAL] " Jaydeep Patil
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