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From: Mike Frysinger via Gdb-patches <gdb-patches@sourceware.org>
To: Jim Wilson <jimw@sifive.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH 1/2] sim: riscv: new port
Date: Wed, 3 Feb 2021 21:38:46 -0500	[thread overview]
Message-ID: <YBteNrWBSUATa8zD@vapier> (raw)
In-Reply-To: <CAFyWVaY19Vev712kE-9aW5vTw7ufz7-qBVAs4XYUi2DCSwUusg@mail.gmail.com>

On 03 Feb 2021 15:50, Jim Wilson wrote:
> We actually have two RISC-V gdb simulators.  The one you originally wrote,
> and a cgen simulator that Embecosm wrote.  I deferred upstreaming your
> simulator in the hope that the cgen simulator might be better, but
> unfortunately the cgen simulator has a serious problem that it can't easily
> support all architecture variations. This is a problem that will only get
> worse as more extensions are added to the architecture.  I don't know if
> the cgen simulator problems are fixable.  So I personally prefer your
> simulator.  But there are others that would like to see the cgen simulator
> go in.  I don't think we can add both of them.  I don't know how to resolve
> that debate.  Plus there is the problem that I'm involved in so much stuff
> that I can't get anything done anymore.  But anyways if there is a vote,
> I'm voting for your simulator.

my plans are to merge this one even if it is simpler & not as complete,
and then drop the cgen one on top of it once we think it's in a good
state.

i have not looked into the cgen issues to say what can be addressed.
tbh, i'm not super familiar with cgen, and have been slowly peeking
at it over time.  i'm sure at this point you know way more than me
about it.

> Your simulator wasn't lost.  It can be found at
>     https://github.com/riscv/riscv-binutils-gdb/tree/fsf-gdb-10.1-with-sim
> This includes your original port, with some minor improvements from Kito
> Cheng and myself, and a number of others.  They are listed in the ChangeLog
> file.  This is known to work with the gcc testsuite, though we primarily
> use qemu for simulator testing so it doesn't get tested very often.  This
> is part of riscv/riscv-gnu-toolchain, and if you do SIM=gdb when building
> and testing a toolchain, it will use gdb sim to run the gcc testsuite.
> 
> Or if you want to start over with a new simulator that is OK too.  We can
> fix it to work with the gcc testsuite just like we fixed the old one.

i'm aware that there's a squashed one with updates not authored by me in
the riscv repos.  i specifically avoided those as the authorship is not
clear and i didn't want to untangle copyright assignments.  so i started
with the last one purely by me and updated it to work with what has been
merged into the upstream tree.  i'm happy to merge fixes you've come up
with since i last did any real work, but i want to make sure to keep them
independent for authorship & copyright assignment purposes.

it's not about me trying to maintain control over it all and refusing to
accept changes i didn't come up with by myself :).  the FSF is picky about
keeping copyrights in line (i'm not complaining, just noting), so i wanted
to start with the things i could confidently attest to.
-mike

  reply	other threads:[~2021-02-04  2:38 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-12 11:18 Mike Frysinger via Gdb-patches
2021-01-12 11:18 ` [PATCH 2/2] riscv: enable gdb/sim integration Mike Frysinger via Gdb-patches
2021-02-04 10:45   ` Andrew Burgess
2021-02-03 23:50 ` [PATCH 1/2] sim: riscv: new port Jim Wilson
2021-02-04  2:38   ` Mike Frysinger via Gdb-patches [this message]
2021-02-04 22:56     ` Jim Wilson
2021-02-04 10:52 ` Andrew Burgess
2021-02-04 14:14 ` Andrew Burgess
2021-02-05  0:04   ` Mike Frysinger via Gdb-patches

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