Re: [PATCH 1/2] sim: riscv: new port

Jim Wilson
2021-02-03T23:51:18Z

We actually have two RISC-V gdb simulators. The one you originally wrote,
and a cgen simulator that Embecosm wrote. I deferred upstreaming your
simulator in the hope that the cgen simulator might be better, but
unfortunately the cgen simulator has a serious problem that it can't easily
support all architecture variations. This is a problem that will only get
worse as more extensions are added to the architecture. I don't know if
the cgen simulator problems are fixable. So I personally prefer your
simulator. But there are others that would like to see the cgen simulator
go in. I don't think we can add both of them. I don't know how to resolve
that debate. Plus there is the problem that I'm involved in so much stuff
that I can't get anything done anymore. But anyways if there is a vote,
I'm voting for your simulator.

Your simulator wasn't lost. It can be found at
https://github.com/riscv/riscv-binutils-gdb/tree/fsf-gdb-10.1-with-sim
This includes your original port, with some minor improvements from Kito
Cheng and myself, and a number of others. They are listed in the ChangeLog
file. This is known to work with the gcc testsuite, though we primarily
use qemu for simulator testing so it doesn't get tested very often. This
is part of riscv/riscv-gnu-toolchain, and if you do SIM=gdb when building
and testing a toolchain, it will use gdb sim to run the gcc testsuite.

Or if you want to start over with a new simulator that is OK too. We can
fix it to work with the gcc testsuite just like we fixed the old one.

Jim