From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: Mike Frysinger <vapier@gentoo.org>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>,
"aburgess@redhat.com" <aburgess@redhat.com>,
Joseph Faulls <Joseph.Faulls@imgtec.com>,
Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Subject: RE: [EXTERNAL] Re: [PATCH v2 1/3] [sim/riscv] Add basic semi-hosting support
Date: Wed, 20 Dec 2023 08:52:05 +0000 [thread overview]
Message-ID: <CWXP265MB5321D3F74A662C172C43EEA88C96A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <ZYJHKRQPrltVVEJo@vapier>
Mike Frysinger <vapier@gentoo.org> writes:
> what specification are you implementing ? newlib is an implementation, not a specification.
I am referring to https://github.com/riscv-software-src/riscv-semihosting/blob/main/riscv-semihosting-spec.adoc. This is still a discussion document and not ratified. The document says "RISC-V semihosting borrows from the design of other publicly available and open source semihosting mechanisms to minimize the development effort required. At some stage, the document referred to "Semihosting for AArch32 and AArch64" (https://github.com/riscv-software-src/riscv-semihosting/blob/de2a56ff73439b1d955e361eb4d35c0e8e453a42/riscv-semihosting-spec.adoc). Looking at the implementation of newlib and picolib, they are following the same specification.
Regards,
Jaydeep
next prev parent reply other threads:[~2023-12-20 8:52 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 13:00 [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and " jaydeep.patil
2023-10-30 13:00 ` [PATCH v2 1/3] [sim/riscv] Add basic " jaydeep.patil
2023-11-29 7:57 ` Mike Frysinger
2023-12-12 17:24 ` Andrew Burgess
2023-12-13 3:43 ` Mike Frysinger
2023-12-18 12:44 ` Andrew Burgess
2023-12-18 23:06 ` Mike Frysinger
2023-12-19 6:13 ` [EXTERNAL] " Jaydeep Patil
2023-12-20 1:45 ` Mike Frysinger
2023-12-20 8:52 ` Jaydeep Patil [this message]
2023-12-12 17:57 ` Andrew Burgess
2023-10-30 13:00 ` [PATCH v2 2/3] [sim/riscv] Add support for compressed integer instruction set jaydeep.patil
2023-11-29 7:58 ` Mike Frysinger
2023-12-19 6:11 ` [EXTERNAL] " Jaydeep Patil
2023-12-20 1:32 ` Mike Frysinger
2023-10-30 13:00 ` [PATCH v2 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-11-13 12:07 ` [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and " Jaydeep Patil
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