From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: Mike Frysinger <vapier@gentoo.org>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>,
"aburgess@redhat.com" <aburgess@redhat.com>,
Joseph Faulls <Joseph.Faulls@imgtec.com>,
Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Subject: RE: [EXTERNAL] Re: [PATCH v2 2/3] [sim/riscv] Add support for compressed integer instruction set
Date: Tue, 19 Dec 2023 06:11:09 +0000 [thread overview]
Message-ID: <CWXP265MB5321A386262A8AC76D78533E8C97A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <ZWbvDQhwlJ6bDjRm@vapier>
Mike Frysinger <vapier@gentoo.org> writes:
> i haven't been keeping up with riscv specs. is the compressed extension finalized ? so you're only implementing official insns in the spec ? i don't think it's appropriate for the sim to implement vendor-specific stuff at this point in time.
The compressed instruction set ("c") is not vendor specific. It has been ratified.
> afaict, there is no relationship between the compression & semi-hosting work.
> these are just two things you're working on ? so they don't really need to be in the same patch series.
Yes, there is no relation between compression & semi-hosting work. The patches are independent and I can re-submit them if needed.
> i'm missing something ... why does there need to be tests in gdb at all here ?
Purpose of riscv-insn-simulation.exp is to test both C extension and semi-hosting. However, I have also added sim specific tests in patch v3.
Regards,
Jaydeep
next prev parent reply other threads:[~2023-12-19 6:11 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 13:00 [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support jaydeep.patil
2023-10-30 13:00 ` [PATCH v2 1/3] [sim/riscv] Add basic " jaydeep.patil
2023-11-29 7:57 ` Mike Frysinger
2023-12-12 17:24 ` Andrew Burgess
2023-12-13 3:43 ` Mike Frysinger
2023-12-18 12:44 ` Andrew Burgess
2023-12-18 23:06 ` Mike Frysinger
2023-12-19 6:13 ` [EXTERNAL] " Jaydeep Patil
2023-12-20 1:45 ` Mike Frysinger
2023-12-20 8:52 ` Jaydeep Patil
2023-12-12 17:57 ` Andrew Burgess
2023-10-30 13:00 ` [PATCH v2 2/3] [sim/riscv] Add support for compressed integer instruction set jaydeep.patil
2023-11-29 7:58 ` Mike Frysinger
2023-12-19 6:11 ` Jaydeep Patil [this message]
2023-12-20 1:32 ` [EXTERNAL] " Mike Frysinger
2023-10-30 13:00 ` [PATCH v2 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-11-13 12:07 ` [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and " Jaydeep Patil
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