Re: [PATCH] riscv: add gdbserver support

[Jim Wilson <jimw@sifive.com>]

On Tue, Jan 21, 2020 at 6:15 PM Guo Ren <guoren@kernel.org> wrote:
> In fact, both T-HEAD XuanTie C910 and Andes 27-series CPU cores claim
> to support vector extensions, which is good for riscv-v extenstion.

I believe the XuanTie C910 part implemented the 0.7.1 draft, I have no
idea what Andes implemented.  SiFive also has vector support in
development.  But my concern here is that we have different chips
implementing different incompatible draft versions of the vector spec.
This is going to be a nightmare to maintain.  These draft versions of
the vector spec never should have been implemented in released
hardware.

> Many complex linux vector development/test-suite need linux/gdb/glibc
> to support the vector-regs' context.

The binutils support is on a branch in a github.com/riscv repo,
waiting for the vector extension to reach its final form.  We are only
planning to upstream support for the official vector extension, not
any of the conflicting draft proposals.  The same could be done for
other parts of the vector support.  We can create branches in the
riscv repos, or we could create branches in upstream repos.  We don't
have to add patches now that may conflict with the official vector
extension support.

As for gdb, it is still the case that no one has made a psabi proposal
to assign dwarf register numbers to the vector registers.

Jim