From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74869 invoked by alias); 22 Jan 2020 06:12:30 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 74861 invoked by uid 89); 22 Jan 2020 06:12:30 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 spammy=071, H*RU:209.85.222.66, HX-Spam-Relays-External:209.85.222.66, nightmare X-HELO: mail-ua1-f66.google.com Received: from mail-ua1-f66.google.com (HELO mail-ua1-f66.google.com) (209.85.222.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 06:12:29 +0000 Received: by mail-ua1-f66.google.com with SMTP id 59so1982074uap.12 for ; Tue, 21 Jan 2020 22:12:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UsrLL7zQihZWmPdZfPvWrX1BrArfBatQZQLq184TBKA=; b=MJKtDuVE90QE6NhGgx7BZR+25znqR8fJ/RbC9tXa2msUSXhjYcX7EV3EdFe3a7LuVq NbxwlkM9HjF9uAGjittkveuO0ebLXt8Pplc9xuqfHRkE6YSrn/SiLibnH2WqUXfJirJI vxuehyS/wxYRAh5z+a9T8GPgagHvVR64nEfAC939Md3RZIUc1DUOjkmLsclL5J9Swi/Q iLURzJ2tUG8OYwRiNMhiBaa4NQTE7UEZ6RY2Kv27AsvR6dAtMHDrgqa8Eb6PmXxdxDLG lmC0/XPx/hP9PdhuOgVv7J3v6oMzLjDJua0W6R3eFEMLRyGWpV9DwIk/B9TT3Dmzm1xW uo7A== MIME-Version: 1.0 References: <00e401d5cb52$63a4d000$2aee7000$@c-sky.com> In-Reply-To: From: Jim Wilson Date: Wed, 22 Jan 2020 06:15:00 -0000 Message-ID: Subject: Re: [PATCH] riscv: add gdbserver support To: Guo Ren Cc: jiangshuai_li@c-sky.com, Maciej Rozycki , Andrew Burgess , gdb-patches@sourceware.org, =?UTF-8?B?5aSP56uL5pa5?= , yunhai_shang Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2020-01/txt/msg00668.txt.bz2 On Tue, Jan 21, 2020 at 6:15 PM Guo Ren wrote: > In fact, both T-HEAD XuanTie C910 and Andes 27-series CPU cores claim > to support vector extensions, which is good for riscv-v extenstion. I believe the XuanTie C910 part implemented the 0.7.1 draft, I have no idea what Andes implemented. SiFive also has vector support in development. But my concern here is that we have different chips implementing different incompatible draft versions of the vector spec. This is going to be a nightmare to maintain. These draft versions of the vector spec never should have been implemented in released hardware. > Many complex linux vector development/test-suite need linux/gdb/glibc > to support the vector-regs' context. The binutils support is on a branch in a github.com/riscv repo, waiting for the vector extension to reach its final form. We are only planning to upstream support for the official vector extension, not any of the conflicting draft proposals. The same could be done for other parts of the vector support. We can create branches in the riscv repos, or we could create branches in upstream repos. We don't have to add patches now that may conflict with the official vector extension support. As for gdb, it is still the case that no one has made a psabi proposal to assign dwarf register numbers to the vector registers. Jim