From: Tsukasa OI via Gdb-patches <gdb-patches@sourceware.org>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Andrew Burgess <aburgess@redhat.com>,
Mike Frysinger <vapier@gentoo.org>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: gdb-patches@sourceware.org
Subject: [PATCH 1/1] sim/riscv: Complete tidying up with SBREAK
Date: Sun, 4 Sep 2022 07:45:06 +0000 [thread overview]
Message-ID: <9397aa661e0b6ba2c02c96f166088387a99c84a8.1662277499.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1662277499.git.research_trasio@irq.a4lg.com>
This commit removes SBREAK-related references on the simulator as it's
renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).
sim/ChangeLog:
* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".
---
sim/riscv/sim-main.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 62f475671c9..30d2f1e1c9a 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FENCE_I:
TRACE_INSN (cpu, "fence.i;");
break;
- case MATCH_SBREAK:
- TRACE_INSN (cpu, "sbreak;");
- /* GDB expects us to step over SBREAK. */
+ case MATCH_EBREAK:
+ TRACE_INSN (cpu, "ebreak;");
+ /* GDB expects us to step over EBREAK. */
sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP);
break;
case MATCH_ECALL:
--
2.34.1
next prev parent reply other threads:[~2022-09-04 7:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-04 7:45 [PATCH 0/1] " Tsukasa OI via Gdb-patches
2022-09-04 7:45 ` Tsukasa OI via Gdb-patches [this message]
2022-09-04 17:07 ` [PATCH 1/1] " Andrew Burgess via Gdb-patches
2022-09-05 8:45 ` Andrew Burgess via Gdb-patches
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