Re: [PATCH 1/1] sim/riscv: Complete tidying up with SBREAK

[Andrew Burgess via Gdb-patches <gdb-patches@sourceware.org>]

* Tsukasa OI <research_trasio@irq.a4lg.com> [2022-09-04 07:45:06 +0000]:

> This commit removes SBREAK-related references on the simulator as it's
> renamed to EBREAK in 2016 (the RISC-V ISA, version 2.1).
> 
> sim/ChangeLog:
> 
> 	* riscv/sim-main.c (execute_i): Use "ebreak" instead of "sbreak".

Approved.  Please go ahead and apply.

Thanks,
Andrew


> ---
>  sim/riscv/sim-main.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 62f475671c9..30d2f1e1c9a 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -583,9 +583,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>      case MATCH_FENCE_I:
>        TRACE_INSN (cpu, "fence.i;");
>        break;
> -    case MATCH_SBREAK:
> -      TRACE_INSN (cpu, "sbreak;");
> -      /* GDB expects us to step over SBREAK.  */
> +    case MATCH_EBREAK:
> +      TRACE_INSN (cpu, "ebreak;");
> +      /* GDB expects us to step over EBREAK.  */
>        sim_engine_halt (sd, cpu, NULL, cpu->pc + 4, sim_stopped, SIM_SIGTRAP);
>        break;
>      case MATCH_ECALL:
> -- 
> 2.34.1
>