From: Yoshinori Sato <ysato@users.sourceforge.jp>
To: gdb-patches@sourceware.org
Subject: sim: h8300 predec special case test
Date: Tue, 04 May 2021 22:38:50 +0900 [thread overview]
Message-ID: <87mtta7h5h.wl-ysato@users.sourceforge.jp> (raw)
In "mov. [bwl] reg, @ -reg", added a special case test
using the same register.
ChangeLog
2021-05-04 Yoshinori Sato <ysato@users.sourceforge.jp>
* movb.s: Add special case predec test.
* movw.s: Likewise.
* movl.s: Likewise.
---
sim/testsuite/h8300/movb.s | 13 +++++++++++--
sim/testsuite/h8300/movl.s | 10 ++++++++++
sim/testsuite/h8300/movw.s | 10 ++++++++++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/sim/testsuite/h8300/movb.s b/sim/testsuite/h8300/movb.s
index 87dcdf3fc40..06d7611b8e0 100644
--- a/sim/testsuite/h8300/movb.s
+++ b/sim/testsuite/h8300/movb.s
@@ -1,4 +1,4 @@
-# Hitachi H8 testcase 'mov.w'
+# Hitachi H8 testcase 'mov.b'
# mach(): h8300h h8300s h8sx
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
@@ -792,6 +792,16 @@ mov_b_reg8_to_predec: ; pre-decrement from register to mem
beq .Lnext48
fail
.Lnext48:
+ ;; Special case in same register
+ ;; CCR confirmation omitted
+ mov.l #byte_dst+1, er1
+ mov.l er1, er0
+ mov.b r0l, @-er0
+ mov.b @byte_dst, r0l
+ cmp.b r1l, r0l
+ beq .Lnext47
+ fail
+.Lnext47:
mov.b #0, r0l
mov.b r0l, @byte_dst ; zero it again for the next use.
@@ -2218,4 +2228,3 @@ mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory
fail1:
fail
-
\ No newline at end of file
diff --git a/sim/testsuite/h8300/movl.s b/sim/testsuite/h8300/movl.s
index dcc392227e6..63a861345e0 100644
--- a/sim/testsuite/h8300/movl.s
+++ b/sim/testsuite/h8300/movl.s
@@ -1282,6 +1282,16 @@ mov_l_reg32_to_predec: ; pre-decrement from register to mem
beq .Lnext48
fail
.Lnext48:
+ ;; Special case in same register
+ ;; CCR confirmation omitted
+ mov.l #long_dst+4, er1
+ mov.l er1, er0
+ mov.l er0, @-er0
+ mov.l @long_dst, er0
+ cmp.l er1, er0
+ beq .Lnext47
+ fail
+.Lnext47:
mov.l #0, er0
mov.l er0, @long_dst ; zero it again for the next use.
diff --git a/sim/testsuite/h8300/movw.s b/sim/testsuite/h8300/movw.s
index b8b09ea8baa..2502b364d85 100644
--- a/sim/testsuite/h8300/movw.s
+++ b/sim/testsuite/h8300/movw.s
@@ -988,6 +988,16 @@ mov_w_reg16_to_predec: ; pre-decrement from register to mem
beq .Lnext48
fail
.Lnext48:
+ ;; Special case in same register
+ ;; CCR confirmation omitted
+ mov.l #word_dst+2, er1
+ mov.l er1, er0
+ mov.w r0, @-er0
+ mov.w @word_dst, r0
+ cmp.w r1, r0
+ beq .Lnext47
+ fail
+.Lnext47:
mov.w #0, r0
mov.w r0, @word_dst ; zero it again for the next use.
--
Yosinori Sato
next reply other threads:[~2021-05-04 13:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-04 13:38 Yoshinori Sato [this message]
2021-05-04 17:47 ` Mike Frysinger via Gdb-patches
2021-05-06 8:14 ` Yoshinori Sato
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