From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id D7k4EHdOkWB5YgAAWB0awg (envelope-from ) for ; Tue, 04 May 2021 09:39:03 -0400 Received: by simark.ca (Postfix, from userid 112) id 2DFC21F11C; Tue, 4 May 2021 09:39:03 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.6 required=5.0 tests=MAILING_LIST_MULTI, RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A9DC21E54D for ; Tue, 4 May 2021 09:39:01 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 087F93958C30; Tue, 4 May 2021 13:39:01 +0000 (GMT) Received: from mail01.asahi-net.or.jp (mail01.asahi-net.or.jp [202.224.55.13]) by sourceware.org (Postfix) with ESMTP id 71A0239540EC for ; Tue, 4 May 2021 13:38:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 71A0239540EC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=ysato@users.sourceforge.jp Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id 82DB73B1DE for ; Tue, 4 May 2021 22:38:55 +0900 (JST) Received: from yo-satoh-debian.ysato.ml (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 851881C03C1 for ; Tue, 4 May 2021 22:38:54 +0900 (JST) Date: Tue, 04 May 2021 22:38:50 +0900 Message-ID: <87mtta7h5h.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: gdb-patches@sourceware.org Subject: sim: h8300 predec special case test User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/27 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" In "mov. [bwl] reg, @ -reg", added a special case test using the same register. ChangeLog 2021-05-04 Yoshinori Sato * movb.s: Add special case predec test. * movw.s: Likewise. * movl.s: Likewise. --- sim/testsuite/h8300/movb.s | 13 +++++++++++-- sim/testsuite/h8300/movl.s | 10 ++++++++++ sim/testsuite/h8300/movw.s | 10 ++++++++++ 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/sim/testsuite/h8300/movb.s b/sim/testsuite/h8300/movb.s index 87dcdf3fc40..06d7611b8e0 100644 --- a/sim/testsuite/h8300/movb.s +++ b/sim/testsuite/h8300/movb.s @@ -1,4 +1,4 @@ -# Hitachi H8 testcase 'mov.w' +# Hitachi H8 testcase 'mov.b' # mach(): h8300h h8300s h8sx # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 @@ -792,6 +792,16 @@ mov_b_reg8_to_predec: ; pre-decrement from register to mem beq .Lnext48 fail .Lnext48: + ;; Special case in same register + ;; CCR confirmation omitted + mov.l #byte_dst+1, er1 + mov.l er1, er0 + mov.b r0l, @-er0 + mov.b @byte_dst, r0l + cmp.b r1l, r0l + beq .Lnext47 + fail +.Lnext47: mov.b #0, r0l mov.b r0l, @byte_dst ; zero it again for the next use. @@ -2218,4 +2228,3 @@ mov_b_abs32_to_abs32: ; 32-bit absolute addr, memory to memory fail1: fail - \ No newline at end of file diff --git a/sim/testsuite/h8300/movl.s b/sim/testsuite/h8300/movl.s index dcc392227e6..63a861345e0 100644 --- a/sim/testsuite/h8300/movl.s +++ b/sim/testsuite/h8300/movl.s @@ -1282,6 +1282,16 @@ mov_l_reg32_to_predec: ; pre-decrement from register to mem beq .Lnext48 fail .Lnext48: + ;; Special case in same register + ;; CCR confirmation omitted + mov.l #long_dst+4, er1 + mov.l er1, er0 + mov.l er0, @-er0 + mov.l @long_dst, er0 + cmp.l er1, er0 + beq .Lnext47 + fail +.Lnext47: mov.l #0, er0 mov.l er0, @long_dst ; zero it again for the next use. diff --git a/sim/testsuite/h8300/movw.s b/sim/testsuite/h8300/movw.s index b8b09ea8baa..2502b364d85 100644 --- a/sim/testsuite/h8300/movw.s +++ b/sim/testsuite/h8300/movw.s @@ -988,6 +988,16 @@ mov_w_reg16_to_predec: ; pre-decrement from register to mem beq .Lnext48 fail .Lnext48: + ;; Special case in same register + ;; CCR confirmation omitted + mov.l #word_dst+2, er1 + mov.l er1, er0 + mov.w r0, @-er0 + mov.w @word_dst, r0 + cmp.w r1, r0 + beq .Lnext47 + fail +.Lnext47: mov.w #0, r0 mov.w r0, @word_dst ; zero it again for the next use. -- Yosinori Sato